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	<title>NURDspace - User contributions [en]</title>
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	<updated>2026-04-19T04:36:51Z</updated>
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	<entry>
		<id>https://nurdspace.nl/index.php?title=FPGA_workshop&amp;diff=5695</id>
		<title>FPGA workshop</title>
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		<updated>2015-05-01T23:32:41Z</updated>

		<summary type="html">&lt;p&gt;Bitlair.nl-eightdot: /* Attending */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Event&lt;br /&gt;
|Name=hands-on FPGA&lt;br /&gt;
|Date=2015/05/02&lt;br /&gt;
|Location=@space&lt;br /&gt;
|Contact=theo&lt;br /&gt;
|Attendees=min 3 max 12&lt;br /&gt;
}}&lt;br /&gt;
A two-day hands-on workshop FPGA programming.&lt;br /&gt;
&lt;br /&gt;
Hardware: an Altera cyclone  FPGA development kit such as Terasic de0 nano (http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&amp;amp;CategoryNo=139&amp;amp;No=593) or (preferably) Bemicro CV ( http://parts.arrow.com/item/detail/arrow-development-tools/bemicrocv#ypJJ).&lt;br /&gt;
&lt;br /&gt;
*note* I&#039;ve tried to order Bemicro CV&#039;s as that would be better value (cyclone V instead of cyclone IV and 128MB instead of 32MB RAM), but the order got bounced. They go in and out of stock  constantly, so i&#039;ll try again later&lt;br /&gt;
&lt;br /&gt;
== Topics include ==&lt;br /&gt;
* Recap of basic logic design principles&lt;br /&gt;
* FPGA hardware architecture, logic blocks, look-up tables, memory and multipliers&lt;br /&gt;
* FPGA resource constraints: routing, logic blocks, IO limitations&lt;br /&gt;
* Hard &amp;amp; Soft IP and licensing&lt;br /&gt;
* Installing Quartus on a linux machine&lt;br /&gt;
* Design project workflow&lt;br /&gt;
* Basic (V)HDL &lt;br /&gt;
* Nios IIe system builder.&lt;br /&gt;
* Altera vs Xilinx vs Lattice vs .....&lt;br /&gt;
&lt;br /&gt;
== Requirements ==&lt;br /&gt;
&lt;br /&gt;
Some understanding of logic circuitry design principles, a supported (Altera) FPGA development kit and access to a (linux) computer for running the Quartus software&lt;br /&gt;
&lt;br /&gt;
== Costs ==&lt;br /&gt;
&lt;br /&gt;
Free as in free beer and free speech, but limited to the consumables that you bring yourself ;-)&lt;br /&gt;
&lt;br /&gt;
== Venue ==&lt;br /&gt;
&lt;br /&gt;
* Diedenoort, Wageningen&lt;br /&gt;
&lt;br /&gt;
== Extra ==&lt;br /&gt;
&lt;br /&gt;
Date and supported development kits are tentative, and will be fixed at least 8 weeks before workshop. If necessary we can organize a group-buy.&lt;br /&gt;
&lt;br /&gt;
If you&#039;re interested in joining please PM me at the0 @ #nurds (irc.oftc.net) OR reply to my mail to the mailing list. It would be useful to know how much you know about digital circuit design as well&lt;br /&gt;
&lt;br /&gt;
== Want to attend ==&lt;br /&gt;
&lt;br /&gt;
* Some other date, not feb 14 [[User:Anus|Anus]] probably +1 (or 2) with some fpga bits and bobs&lt;br /&gt;
* dreamer&lt;br /&gt;
* ..&lt;br /&gt;
===Attending===&lt;br /&gt;
{{#ask: [[Category:Members]] [[Attending::{{PAGENAME}}]] | format=ul }}&lt;br /&gt;
Eightdot&lt;/div&gt;</summary>
		<author><name>Bitlair.nl-eightdot</name></author>
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