<?xml version="1.0"?>
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	<id>https://nurdspace.nl/api.php?action=feedcontributions&amp;feedformat=atom&amp;user=Zmatt</id>
	<title>NURDspace - User contributions [en]</title>
	<link rel="self" type="application/atom+xml" href="https://nurdspace.nl/api.php?action=feedcontributions&amp;feedformat=atom&amp;user=Zmatt"/>
	<link rel="alternate" type="text/html" href="https://nurdspace.nl/Special:Contributions/Zmatt"/>
	<updated>2026-04-19T15:50:56Z</updated>
	<subtitle>User contributions</subtitle>
	<generator>MediaWiki 1.39.4</generator>
	<entry>
		<id>https://nurdspace.nl/index.php?title=NEN_Nurd_en_Nieuw_2023&amp;diff=13812</id>
		<title>NEN Nurd en Nieuw 2023</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=NEN_Nurd_en_Nieuw_2023&amp;diff=13812"/>
		<updated>2023-12-26T02:47:15Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Attendees */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Event&lt;br /&gt;
|Name=NEN Nurd en Nieuw 2023&lt;br /&gt;
|Date=December 2023&lt;br /&gt;
|DateEnd=January 2024&lt;br /&gt;
|Location=spaaaace&lt;br /&gt;
|Contact=irc obv&lt;br /&gt;
}}&lt;br /&gt;
yay the year is over&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
== Attendees ==&lt;br /&gt;
&lt;br /&gt;
* buZz&lt;br /&gt;
* Thomas (+lorenzo)&lt;br /&gt;
* Joel (+2 4pooters)&lt;br /&gt;
* Tahtkev&lt;br /&gt;
* zmatt&lt;br /&gt;
* ??&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=Bb-leds&amp;diff=13055</id>
		<title>Bb-leds</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=Bb-leds&amp;diff=13055"/>
		<updated>2023-01-01T18:11:07Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BB-leds&lt;br /&gt;
|Skills=Electronics,&lt;br /&gt;
|Status=Getting parts&lt;br /&gt;
|Niche=Hardware&lt;br /&gt;
|Purpose=Fun&lt;br /&gt;
|Picture=bb-leds-power.jpg&lt;br /&gt;
|Tool=No&lt;br /&gt;
|Location=shelves next to studio&lt;br /&gt;
|Category=General&lt;br /&gt;
}}&lt;br /&gt;
Monochrome LED tickers donated from ]LAG[&lt;br /&gt;
* 2 boards * 3 text lines * 7 rows * 90 columns&lt;br /&gt;
* Boards have been reverse-engineered (TODO document on wiki)&lt;br /&gt;
* One board is missing the PNP transistor for one of the seven rows&lt;br /&gt;
&lt;br /&gt;
2023-01-01 First attempt to power up one of the boards (the one that isn&#039;t missing one of its transistors) using variable power supply failed, high current draw (0.5A) was observed at only a few volts. One of the two tantalum caps is the main suspect, further investigation needed. Other board not yet tested.&lt;br /&gt;
&lt;br /&gt;
== beaglebone ==&lt;br /&gt;
&lt;br /&gt;
2022-12-31 Flashed with a basic debian bullseye system.&lt;br /&gt;
* hostname: &amp;lt;code&amp;gt;bb-leds&amp;lt;/code&amp;gt;&lt;br /&gt;
* login: &amp;lt;code&amp;gt;debian&amp;lt;/code&amp;gt;&lt;br /&gt;
* password: &amp;lt;code&amp;gt;777&amp;lt;/code&amp;gt;&lt;br /&gt;
&lt;br /&gt;
This beaglebone is missing its mini-usb port but can be powered via the P9 header e.g. using included cable (see photo).&lt;br /&gt;
&lt;br /&gt;
For reference, the power pins of the beaglebone:&lt;br /&gt;
* P9.01 + P9.02 = GND&lt;br /&gt;
* P9.03 + P9.04 = 3.3V out (unused)&lt;br /&gt;
* P9.05 + P9.06 = 5V in&lt;br /&gt;
* P9.07 + P9.08 = 5V out (to level shifter)&lt;br /&gt;
&lt;br /&gt;
== level shifter ==&lt;br /&gt;
&lt;br /&gt;
A 3.3V to 5V level shifter is needed (3 signals per board, can probably be optimized to 4 signals total for both boards if they&#039;re driven synchronously). As a temporary hack a beestore pro mini from [[User:flok]] has been programmed to act as a 6-ch level shifter with following pinout:&lt;br /&gt;
* PC0 (&amp;quot;A0&amp;quot;) → PB0 (&amp;quot;D8&amp;quot;)&lt;br /&gt;
* PC1 (&amp;quot;A1&amp;quot;) → PB1 (&amp;quot;D9&amp;quot;)&lt;br /&gt;
* PC2 (&amp;quot;A2&amp;quot;) → PB2 (&amp;quot;D10&amp;quot;)&lt;br /&gt;
* PC3 (&amp;quot;A3&amp;quot;) → PB3 (&amp;quot;D11&amp;quot;)&lt;br /&gt;
* PC4 (&amp;quot;A4/SCL&amp;quot;) → PB4 (&amp;quot;D12&amp;quot;)&lt;br /&gt;
* PC5 (&amp;quot;A5/SDA&amp;quot;) → PB5 (&amp;quot;D13&amp;quot;)&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=Bb-leds&amp;diff=13054</id>
		<title>Bb-leds</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=Bb-leds&amp;diff=13054"/>
		<updated>2023-01-01T18:06:44Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: fix photo&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BB-leds&lt;br /&gt;
|Skills=Electronics,&lt;br /&gt;
|Status=Getting parts&lt;br /&gt;
|Niche=Hardware&lt;br /&gt;
|Purpose=Fun&lt;br /&gt;
|Picture=bb-leds-power.jpg&lt;br /&gt;
|Tool=No&lt;br /&gt;
|Location=shelves next to studio&lt;br /&gt;
|Category=General&lt;br /&gt;
}}&lt;br /&gt;
Monochrome LED tickers donated from ]LAG[&lt;br /&gt;
* 2 boards * 3 text lines * 7 rows * 90 columns&lt;br /&gt;
* Boards have been reverse-engineered (TODO document on wiki)&lt;br /&gt;
* One board is missing the PNP transistor for one of the seven rows&lt;br /&gt;
&lt;br /&gt;
== beaglebone ==&lt;br /&gt;
&lt;br /&gt;
2022-12-31 Flashed with a basic debian bullseye system.&lt;br /&gt;
* hostname: &amp;lt;code&amp;gt;bb-leds&amp;lt;/code&amp;gt;&lt;br /&gt;
* login: &amp;lt;code&amp;gt;debian&amp;lt;/code&amp;gt;&lt;br /&gt;
* password: &amp;lt;code&amp;gt;777&amp;lt;/code&amp;gt;&lt;br /&gt;
&lt;br /&gt;
This beaglebone is missing its mini-usb port but can be powered via the P9 header e.g. using included cable (see photo).&lt;br /&gt;
&lt;br /&gt;
For reference, the power pins of the beaglebone:&lt;br /&gt;
* P9.01 + P9.02 = GND&lt;br /&gt;
* P9.03 + P9.04 = 3.3V out (unused)&lt;br /&gt;
* P9.05 + P9.06 = 5V in&lt;br /&gt;
* P9.07 + P9.08 = 5V out (to level shifter)&lt;br /&gt;
&lt;br /&gt;
== level shifter ==&lt;br /&gt;
&lt;br /&gt;
A 3.3V to 5V level shifter is needed (3 signals per board, can probably be optimized to 4 signals total for both boards if they&#039;re driven synchronously). As a temporary hack a beestore pro mini from [[User:flok]] has been programmed to act as a 6-ch level shifter with pinout:&lt;br /&gt;
* PC0 (&amp;quot;A0&amp;quot;) → PB0 (&amp;quot;D8&amp;quot;)&lt;br /&gt;
* PC1 (&amp;quot;A1&amp;quot;) → PB1 (&amp;quot;D9&amp;quot;)&lt;br /&gt;
* PC2 (&amp;quot;A2&amp;quot;) → PB2 (&amp;quot;D10&amp;quot;)&lt;br /&gt;
* PC3 (&amp;quot;A3&amp;quot;) → PB3 (&amp;quot;D11&amp;quot;)&lt;br /&gt;
* PC4 (&amp;quot;A4/SCL&amp;quot;) → PB4 (&amp;quot;D12&amp;quot;)&lt;br /&gt;
* PC5 (&amp;quot;A5/SDA&amp;quot;) → PB5 (&amp;quot;D13&amp;quot;)&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=Bb-leds&amp;diff=13053</id>
		<title>Bb-leds</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=Bb-leds&amp;diff=13053"/>
		<updated>2023-01-01T18:03:03Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* beaglebone */ photo and note on pinout of power&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BB-leds&lt;br /&gt;
|Skills=Electronics,&lt;br /&gt;
|Status=Getting parts&lt;br /&gt;
|Niche=Hardware&lt;br /&gt;
|Purpose=Fun&lt;br /&gt;
|Tool=No&lt;br /&gt;
|Location=shelves next to studio&lt;br /&gt;
|Category=General&lt;br /&gt;
}}&lt;br /&gt;
&lt;br /&gt;
Monochrome LED tickers donated from ]LAG[&lt;br /&gt;
* 2 boards * 3 text lines * 7 rows * 90 columns&lt;br /&gt;
* Boards have been reverse-engineered (TODO document on wiki)&lt;br /&gt;
* One board is missing the PNP transistor for one of the seven rows&lt;br /&gt;
&lt;br /&gt;
== beaglebone ==&lt;br /&gt;
&lt;br /&gt;
[[File:bb-leds-power.jpg|300px|right]]&lt;br /&gt;
&lt;br /&gt;
2022-12-31 Flashed with a basic debian bullseye system.&lt;br /&gt;
* hostname: &amp;lt;code&amp;gt;bb-leds&amp;lt;/code&amp;gt;&lt;br /&gt;
* login: &amp;lt;code&amp;gt;debian&amp;lt;/code&amp;gt;&lt;br /&gt;
* password: &amp;lt;code&amp;gt;777&amp;lt;/code&amp;gt;&lt;br /&gt;
&lt;br /&gt;
This beaglebone is missing its mini-usb port but can be powered via the P9 header e.g. using included cable (see photo).&lt;br /&gt;
&lt;br /&gt;
For reference, the power pins of the beaglebone:&lt;br /&gt;
* P9.01 + P9.02 = GND&lt;br /&gt;
* P9.03 + P9.04 = 3.3V out (unused)&lt;br /&gt;
* P9.05 + P9.06 = 5V in&lt;br /&gt;
* P9.07 + P9.08 = 5V out (to level shifter)&lt;br /&gt;
&lt;br /&gt;
== level shifter ==&lt;br /&gt;
&lt;br /&gt;
A 3.3V to 5V level shifter is needed (3 signals per board, can probably be optimized to 4 signals total for both boards if they&#039;re driven synchronously). As a temporary hack a beestore pro mini from [[User:flok]] has been programmed to act as a 6-ch level shifter with pinout:&lt;br /&gt;
* PC0 (&amp;quot;A0&amp;quot;) → PB0 (&amp;quot;D8&amp;quot;)&lt;br /&gt;
* PC1 (&amp;quot;A1&amp;quot;) → PB1 (&amp;quot;D9&amp;quot;)&lt;br /&gt;
* PC2 (&amp;quot;A2&amp;quot;) → PB2 (&amp;quot;D10&amp;quot;)&lt;br /&gt;
* PC3 (&amp;quot;A3&amp;quot;) → PB3 (&amp;quot;D11&amp;quot;)&lt;br /&gt;
* PC4 (&amp;quot;A4/SCL&amp;quot;) → PB4 (&amp;quot;D12&amp;quot;)&lt;br /&gt;
* PC5 (&amp;quot;A5/SDA&amp;quot;) → PB5 (&amp;quot;D13&amp;quot;)&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=File:Bb-leds-power.jpg&amp;diff=13052</id>
		<title>File:Bb-leds-power.jpg</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=File:Bb-leds-power.jpg&amp;diff=13052"/>
		<updated>2023-01-01T17:53:47Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: powering a beaglebone via the P9 header&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;powering a beaglebone via the P9 header&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=Bb-leds&amp;diff=13051</id>
		<title>Bb-leds</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=Bb-leds&amp;diff=13051"/>
		<updated>2023-01-01T17:44:21Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BB-leds&lt;br /&gt;
|Skills=Electronics,&lt;br /&gt;
|Status=Getting parts&lt;br /&gt;
|Niche=Hardware&lt;br /&gt;
|Purpose=Fun&lt;br /&gt;
|Tool=No&lt;br /&gt;
|Location=shelves next to studio&lt;br /&gt;
|Category=General&lt;br /&gt;
}}&lt;br /&gt;
&lt;br /&gt;
Monochrome LED tickers donated from ]LAG[&lt;br /&gt;
* 2 boards * 3 text lines * 7 rows * 90 columns&lt;br /&gt;
* Boards have been reverse-engineered (TODO document on wiki)&lt;br /&gt;
* One board is missing the PNP transistor for one of the seven rows&lt;br /&gt;
&lt;br /&gt;
== beaglebone ==&lt;br /&gt;
&lt;br /&gt;
2022-12-31 Flashed with a basic debian bullseye system.&lt;br /&gt;
* hostname: &amp;lt;code&amp;gt;bb-leds&amp;lt;/code&amp;gt;&lt;br /&gt;
* login: &amp;lt;code&amp;gt;debian&amp;lt;/code&amp;gt;&lt;br /&gt;
* password: &amp;lt;code&amp;gt;777&amp;lt;/code&amp;gt;&lt;br /&gt;
&lt;br /&gt;
This beaglebone is missing its mini-usb port but can be powered via the P9 header using included cable (TODO insert photo)&lt;br /&gt;
&lt;br /&gt;
== level shifter ==&lt;br /&gt;
&lt;br /&gt;
A 3.3V to 5V level shifter is needed (3 signals per board, can probably be optimized to 4 signals total for both boards if they&#039;re driven synchronously). As a temporary hack a beestore pro mini from [[User:flok]] has been programmed to act as a 6-ch level shifter with pinout:&lt;br /&gt;
* PC0 (&amp;quot;A0&amp;quot;) → PB0 (&amp;quot;D8&amp;quot;)&lt;br /&gt;
* PC1 (&amp;quot;A1&amp;quot;) → PB1 (&amp;quot;D9&amp;quot;)&lt;br /&gt;
* PC2 (&amp;quot;A2&amp;quot;) → PB2 (&amp;quot;D10&amp;quot;)&lt;br /&gt;
* PC3 (&amp;quot;A3&amp;quot;) → PB3 (&amp;quot;D11&amp;quot;)&lt;br /&gt;
* PC4 (&amp;quot;A4/SCL&amp;quot;) → PB4 (&amp;quot;D12&amp;quot;)&lt;br /&gt;
* PC5 (&amp;quot;A5/SDA&amp;quot;) → PB5 (&amp;quot;D13&amp;quot;)&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=NURD%26New&amp;diff=13012</id>
		<title>NURD&amp;New</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=NURD%26New&amp;diff=13012"/>
		<updated>2022-12-23T16:51:40Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Attending */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Event&lt;br /&gt;
|Name=NYE NURDs 2023 edition!&lt;br /&gt;
|Date=2022/12/31&lt;br /&gt;
|DateEnd=2022/01/01&lt;br /&gt;
|Location=Spaaaace&lt;br /&gt;
|Contact=User:Tahtkev&lt;br /&gt;
|Attendees=tahtkev&lt;br /&gt;
}}&lt;br /&gt;
Party in to the new year!&lt;br /&gt;
&lt;br /&gt;
Start: 19:00 (earlier if you want to eat @ space obviously)&lt;br /&gt;
&lt;br /&gt;
End: ~12:00 next day&lt;br /&gt;
&lt;br /&gt;
Start &amp;amp; End arent hard times, but this will guarantee someone is there...&lt;br /&gt;
&lt;br /&gt;
=Music=&lt;br /&gt;
TBD&lt;br /&gt;
&lt;br /&gt;
=Consumeables=&lt;br /&gt;
* space has MATE-MATE&lt;br /&gt;
* some crates of the finest German grainsmoothies provided by Tahtkev (maybe even tap)&lt;br /&gt;
* BYO spirits&lt;br /&gt;
&lt;br /&gt;
=BeforeAfterDuring=&lt;br /&gt;
TBD&lt;br /&gt;
&lt;br /&gt;
=Attending=&lt;br /&gt;
* [[User:R3boot|R3boot]] ([[User talk:R3boot|talk]]) -- party? PARTY!&lt;br /&gt;
* [[User:Buzz|buZz]] ([[User talk:Buzz|talk]]) 11:31, 21 December 2022 (CET)&lt;br /&gt;
* [[User:Zmatt|zmatt]]&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=10870</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=10870"/>
		<updated>2021-10-09T20:17:49Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Big buttons */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Beaglebones.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated BeagleBones seek projects that can give their life meaning.&#039;&#039;&#039; ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do).&lt;br /&gt;
&lt;br /&gt;
Don&#039;t be afraid to play with them, or use one in a project! That&#039;s what they&#039;re for!&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Do you want a 14-channel 100 Msps logic analyzer? Just run [https://beaglelogic.readthedocs.io/en/latest/ BeagleLogic] on a BeagleBone!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
Also, check out my [https://github.com/mvduin/py-uio/#uio_pruss py-uio] project for directly working with the PRU subsystem (and various other peripherals) from python code. Poke me on IRC if you have questions, zmatt in #nurds (OFTC) and #beagle (Libera.chat).&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
There are currently several donated BeagleBone Black (rev C) boards with minor defects, donated by [[User:zmatt|my]] employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]:&lt;br /&gt;
* &amp;quot;boner&amp;quot;. Has 3.3V regulator patch, battery header soldered on, and shown running on battery at the top of the page. One I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
* &amp;quot;ham-015&amp;quot;. eMMC is dead.&lt;br /&gt;
* &amp;quot;[[bb-leds]]&amp;quot; (007357+1650). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;8m-094&amp;quot;. eMMC is dead. Has 3.3V regulator patch, battery header soldered on.&lt;br /&gt;
* &amp;quot;licht-gebakken&amp;quot;. It&#039;s perfectly fine. No, really, I haven&#039;t noticed any problems with it.&lt;br /&gt;
* &amp;quot;[[Not-A-Phone|not-a-phone]]&amp;quot;. Idiot customer connected a phone line to the Ethernet port. PHY still works &#039;&#039;mostly&#039;&#039;, but link detection is wonky. Ethernet works if connected at power on, but hotplugging requires a tiny script (which has been installed) that periodically resets the PHY whenever network is down.&lt;br /&gt;
* &amp;quot;dead-pin-16&amp;quot;. BeagleBone appears to have a production fault: cpu pin 16 (GPIO 1.16) appears to be internally shorted to 3.3V, and attempting to drive it low results in more than 100 mA of current. It has been disconnected from P9.15 by desoldering R160, and P9.15 remains usable thanks to its connection to cpu pin 34 (GPIO 2.00).&lt;br /&gt;
* &amp;quot;ham-059&amp;quot; (007270+1650). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* unlabeled (005857+1651). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;julia&amp;quot; (XAN004945). eMMC is dead. Has 3.3V regulator patch.&lt;br /&gt;
* &amp;quot;8c-132&amp;quot; (005670+1634). eMMC is dead.&lt;br /&gt;
* unlabeled (000010+1720). eMMC is dead.&lt;br /&gt;
* unlabeled (002474+1823). unclear ethernet issues. worked fine on one switch, consistently didn&#039;t work on another switch.&lt;br /&gt;
* &amp;quot;8c-399&amp;quot; (003876+1823). expansion header pins P8.07-10 are solder blobbed together.&lt;br /&gt;
* unlabeled (004847+1850). sd card slot does not work.&lt;br /&gt;
* &amp;quot;8c-186&amp;quot; (004671+1729). No obvious problem, but has probably been exposed to ESD.&lt;br /&gt;
* &amp;quot;8c-421&amp;quot; (006510+1823). No obvious problem, but has probably been exposed to ESD.&lt;br /&gt;
* &amp;quot;8c-599&amp;quot; (000385+1838). No obvious problem, but has probably been exposed to ESD.&lt;br /&gt;
&lt;br /&gt;
The BeagleBones with dead (worn out) eMMC need to boot from μSD card instead, or netboot if you&#039;re feeling adventurous.&lt;br /&gt;
&lt;br /&gt;
When the USB mini-B port is missing, the beaglebone can be powered via 5V barrel jack or via expansion header P9 (connect P9.01 and/or P9.02 to ground, connect P9.05 and/or P9.06 to 5V)&lt;br /&gt;
&lt;br /&gt;
The &amp;quot;3.3V regulator patch&amp;quot; means the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; &amp;lt;strike&amp;gt;in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft&amp;lt;/strike&amp;gt; maybe still somewhere in the space.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed with a basic firmware image (debian stretch with customizations). You can reach it with &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777. There is a README file in the home directory, I might also put more details here if I get less lazy.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host port inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 1kΩ - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Supports Wayland but not X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=10869</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=10869"/>
		<updated>2021-10-09T20:10:42Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* TL;DR */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Beaglebones.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated BeagleBones seek projects that can give their life meaning.&#039;&#039;&#039; ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do).&lt;br /&gt;
&lt;br /&gt;
Don&#039;t be afraid to play with them, or use one in a project! That&#039;s what they&#039;re for!&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Do you want a 14-channel 100 Msps logic analyzer? Just run [https://beaglelogic.readthedocs.io/en/latest/ BeagleLogic] on a BeagleBone!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
Also, check out my [https://github.com/mvduin/py-uio/#uio_pruss py-uio] project for directly working with the PRU subsystem (and various other peripherals) from python code. Poke me on IRC if you have questions, zmatt in #nurds (OFTC) and #beagle (Libera.chat).&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
There are currently several donated BeagleBone Black (rev C) boards with minor defects, donated by [[User:zmatt|my]] employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]:&lt;br /&gt;
* &amp;quot;boner&amp;quot;. Has 3.3V regulator patch, battery header soldered on, and shown running on battery at the top of the page. One I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
* &amp;quot;ham-015&amp;quot;. eMMC is dead.&lt;br /&gt;
* &amp;quot;[[bb-leds]]&amp;quot; (007357+1650). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;8m-094&amp;quot;. eMMC is dead. Has 3.3V regulator patch, battery header soldered on.&lt;br /&gt;
* &amp;quot;licht-gebakken&amp;quot;. It&#039;s perfectly fine. No, really, I haven&#039;t noticed any problems with it.&lt;br /&gt;
* &amp;quot;[[Not-A-Phone|not-a-phone]]&amp;quot;. Idiot customer connected a phone line to the Ethernet port. PHY still works &#039;&#039;mostly&#039;&#039;, but link detection is wonky. Ethernet works if connected at power on, but hotplugging requires a tiny script (which has been installed) that periodically resets the PHY whenever network is down.&lt;br /&gt;
* &amp;quot;dead-pin-16&amp;quot;. BeagleBone appears to have a production fault: cpu pin 16 (GPIO 1.16) appears to be internally shorted to 3.3V, and attempting to drive it low results in more than 100 mA of current. It has been disconnected from P9.15 by desoldering R160, and P9.15 remains usable thanks to its connection to cpu pin 34 (GPIO 2.00).&lt;br /&gt;
* &amp;quot;ham-059&amp;quot; (007270+1650). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* unlabeled (005857+1651). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;julia&amp;quot; (XAN004945). eMMC is dead. Has 3.3V regulator patch.&lt;br /&gt;
* &amp;quot;8c-132&amp;quot; (005670+1634). eMMC is dead.&lt;br /&gt;
* unlabeled (000010+1720). eMMC is dead.&lt;br /&gt;
* unlabeled (002474+1823). unclear ethernet issues. worked fine on one switch, consistently didn&#039;t work on another switch.&lt;br /&gt;
* &amp;quot;8c-399&amp;quot; (003876+1823). expansion header pins P8.07-10 are solder blobbed together.&lt;br /&gt;
* unlabeled (004847+1850). sd card slot does not work.&lt;br /&gt;
* &amp;quot;8c-186&amp;quot; (004671+1729). No obvious problem, but has probably been exposed to ESD.&lt;br /&gt;
* &amp;quot;8c-421&amp;quot; (006510+1823). No obvious problem, but has probably been exposed to ESD.&lt;br /&gt;
* &amp;quot;8c-599&amp;quot; (000385+1838). No obvious problem, but has probably been exposed to ESD.&lt;br /&gt;
&lt;br /&gt;
The BeagleBones with dead (worn out) eMMC need to boot from μSD card instead, or netboot if you&#039;re feeling adventurous.&lt;br /&gt;
&lt;br /&gt;
When the USB mini-B port is missing, the beaglebone can be powered via 5V barrel jack or via expansion header P9 (connect P9.01 and/or P9.02 to ground, connect P9.05 and/or P9.06 to 5V)&lt;br /&gt;
&lt;br /&gt;
The &amp;quot;3.3V regulator patch&amp;quot; means the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; &amp;lt;strike&amp;gt;in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft&amp;lt;/strike&amp;gt; maybe still somewhere in the space.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed with a basic firmware image (debian stretch with customizations). You can reach it with &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777. There is a README file in the home directory, I might also put more details here if I get less lazy.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host port inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Supports Wayland but not X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=10868</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=10868"/>
		<updated>2021-10-09T20:07:07Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Description */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Beaglebones.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated BeagleBones seek projects that can give their life meaning.&#039;&#039;&#039; ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do).&lt;br /&gt;
&lt;br /&gt;
Don&#039;t be afraid to play with them, or use one in a project! That&#039;s what they&#039;re for!&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Do you want a 14-channel 100 Msps logic analyzer? Just run [https://beaglelogic.readthedocs.io/en/latest/ BeagleLogic] on a BeagleBone!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
Also, check out my [https://github.com/mvduin/py-uio/#uio_pruss py-uio] project for directly working with the PRU subsystem (and various other peripherals) from python code. Poke me on IRC if you have questions.&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
There are currently several donated BeagleBone Black (rev C) boards with minor defects, donated by [[User:zmatt|my]] employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]:&lt;br /&gt;
* &amp;quot;boner&amp;quot;. Has 3.3V regulator patch, battery header soldered on, and shown running on battery at the top of the page. One I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
* &amp;quot;ham-015&amp;quot;. eMMC is dead.&lt;br /&gt;
* &amp;quot;[[bb-leds]]&amp;quot; (007357+1650). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;8m-094&amp;quot;. eMMC is dead. Has 3.3V regulator patch, battery header soldered on.&lt;br /&gt;
* &amp;quot;licht-gebakken&amp;quot;. It&#039;s perfectly fine. No, really, I haven&#039;t noticed any problems with it.&lt;br /&gt;
* &amp;quot;[[Not-A-Phone|not-a-phone]]&amp;quot;. Idiot customer connected a phone line to the Ethernet port. PHY still works &#039;&#039;mostly&#039;&#039;, but link detection is wonky. Ethernet works if connected at power on, but hotplugging requires a tiny script (which has been installed) that periodically resets the PHY whenever network is down.&lt;br /&gt;
* &amp;quot;dead-pin-16&amp;quot;. BeagleBone appears to have a production fault: cpu pin 16 (GPIO 1.16) appears to be internally shorted to 3.3V, and attempting to drive it low results in more than 100 mA of current. It has been disconnected from P9.15 by desoldering R160, and P9.15 remains usable thanks to its connection to cpu pin 34 (GPIO 2.00).&lt;br /&gt;
* &amp;quot;ham-059&amp;quot; (007270+1650). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* unlabeled (005857+1651). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;julia&amp;quot; (XAN004945). eMMC is dead. Has 3.3V regulator patch.&lt;br /&gt;
* &amp;quot;8c-132&amp;quot; (005670+1634). eMMC is dead.&lt;br /&gt;
* unlabeled (000010+1720). eMMC is dead.&lt;br /&gt;
* unlabeled (002474+1823). unclear ethernet issues. worked fine on one switch, consistently didn&#039;t work on another switch.&lt;br /&gt;
* &amp;quot;8c-399&amp;quot; (003876+1823). expansion header pins P8.07-10 are solder blobbed together.&lt;br /&gt;
* unlabeled (004847+1850). sd card slot does not work.&lt;br /&gt;
* &amp;quot;8c-186&amp;quot; (004671+1729). No obvious problem, but has probably been exposed to ESD.&lt;br /&gt;
* &amp;quot;8c-421&amp;quot; (006510+1823). No obvious problem, but has probably been exposed to ESD.&lt;br /&gt;
* &amp;quot;8c-599&amp;quot; (000385+1838). No obvious problem, but has probably been exposed to ESD.&lt;br /&gt;
&lt;br /&gt;
The BeagleBones with dead (worn out) eMMC need to boot from μSD card instead, or netboot if you&#039;re feeling adventurous.&lt;br /&gt;
&lt;br /&gt;
When the USB mini-B port is missing, the beaglebone can be powered via 5V barrel jack or via expansion header P9 (connect P9.01 and/or P9.02 to ground, connect P9.05 and/or P9.06 to 5V)&lt;br /&gt;
&lt;br /&gt;
The &amp;quot;3.3V regulator patch&amp;quot; means the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; &amp;lt;strike&amp;gt;in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft&amp;lt;/strike&amp;gt; maybe still somewhere in the space.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed with a basic firmware image (debian stretch with customizations). You can reach it with &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777. There is a README file in the home directory, I might also put more details here if I get less lazy.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host port inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Supports Wayland but not X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=NurdINN_2021&amp;diff=10821</id>
		<title>NurdINN 2021</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=NurdINN_2021&amp;diff=10821"/>
		<updated>2021-09-15T18:15:22Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Coming */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Event&lt;br /&gt;
|Name=NurdINN 2021 #1&lt;br /&gt;
|Date=2021/10/07&lt;br /&gt;
|DateEnd=2021/10/10&lt;br /&gt;
|Location=Spaaaace&lt;br /&gt;
|Contact=stop&lt;br /&gt;
}}&lt;br /&gt;
Time for another nurdinn! The first &#039;big one&#039; of 2021.&lt;br /&gt;
&lt;br /&gt;
== Coming ==&lt;br /&gt;
&lt;br /&gt;
* buZz&lt;br /&gt;
* dreamer&lt;br /&gt;
* Anus&lt;br /&gt;
* Psy0rz&lt;br /&gt;
* [[User:zmatt|zmatt]]&lt;br /&gt;
*&lt;br /&gt;
* you?&lt;br /&gt;
&lt;br /&gt;
== Potential topics? ==&lt;br /&gt;
&lt;br /&gt;
=== watch scorpion ===&lt;br /&gt;
&lt;br /&gt;
Seemingly hilarious, netflix show about &#039;hackers helping gov&#039; , see https://www.youtube.com/watch?v=lcb62SN4TEA&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=LanBox&amp;diff=10495</id>
		<title>LanBox</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=LanBox&amp;diff=10495"/>
		<updated>2020-07-23T02:37:58Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: Update links&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Inventory&lt;br /&gt;
|Name=LanBox-LCX&lt;br /&gt;
|Picture=LanBox-LCX.jpg&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Infrastructure&lt;br /&gt;
|Hostname=lanbox&lt;br /&gt;
}}&lt;br /&gt;
== Description ==&lt;br /&gt;
This networked box controls the DMX lights which illuminate the space. The LanBox-LCX gets its commands from [[SpaceBot]].&lt;br /&gt;
&lt;br /&gt;
* https://www.lanbox.com/lanbox-lcx-eu-model.html&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
== Applications ==&lt;br /&gt;
* http://pastebin.com/EYN9wAhz&lt;br /&gt;
&lt;br /&gt;
== Features ==&lt;br /&gt;
The LanBox is typically controlled via a simple ascii protocol via TCP port 777 (max 5 connections), USB-serial, or MIDI-SysEx. If the last firmware upload was done via USB then it will consider that to be its console stream, otherwise it has a separate console on TCP port 778 (1 connection).&lt;br /&gt;
* [http://support.lanbox.com/Manuals/LanBox%20Reference%203.04.pdf command reference]&lt;br /&gt;
It also supports a variety of other MIDI messages and can broadcast/receive data via UDP. It supports up to 31 layers, each with an independent sequencer. Up to 3072 channels can be enabled across all layers combined, each with an independent fader. The layers are merged into the mixer buffer according to their configured mix-mode, and up to 512 channels can be output via DMX (freely selectable from the mixer buffer and with post-processing such as curve-mapping and slope-limiting).&lt;br /&gt;
&lt;br /&gt;
DMX in and UDP in can be mapped to a layer or directly into the mixer. Some misc other stuff can optionally also be mapped into the mixer, such as its 8 analog inputs, clock (NTP), and MIDI timecode, and its 8 digital outputs can be controlled directly by mixer channels. The sequencers can set channels (with or without fade), control other layers, send arbitrary MIDI messages, bit-bang serial data over some or all of the digital outputs (independently), etc.&lt;br /&gt;
&lt;br /&gt;
== Internals (hardware) ==&lt;br /&gt;
* [http://www.keil.com/dd/docs/datashts/infineon/c165utah_ds.pdf C165UTAH] 16-bit cpu&lt;br /&gt;
** 36 MHz (18 MIPS)&lt;br /&gt;
** 3 KB internal SRAM (cpu regs and stack are allocated here)&lt;br /&gt;
** USB device port&lt;br /&gt;
** high-speed UART, used for DMX in/out&lt;br /&gt;
** SPI, connects to A/D converter ([http://www.ti.com/lit/ds/symlink/tlc1543.pdf TLC1543C])&lt;br /&gt;
** [https://en.wikipedia.org/wiki/ISDN-oriented_Modular_Interface IOM-2] interface (not connected)&lt;br /&gt;
** JTAG debug support&lt;br /&gt;
** the usual bunch of timers and GPIO&lt;br /&gt;
** external bus interface controller&lt;br /&gt;
* Non-multiplexed bus (22-bit address + 16-bit data) connects to:&lt;br /&gt;
** 1 MB SRAM (max 2 MB supported)&lt;br /&gt;
** 1 MB flash (max 4 MB supported)&lt;br /&gt;
** 10base-T ethernet controller ([http://www.cirrus.com/jp/pubs/proDatasheet/CS8900A_F5.pdf CS8900A])&lt;br /&gt;
** UART ([http://www.ti.com/lit/ds/symlink/tl16c550c.pdf TL16C550C]), used for MIDI in/out&lt;br /&gt;
** digital outputs ([http://www.nxp.com/documents/data_sheet/74AHC_AHCT574.pdf 74AHCT574])&lt;br /&gt;
&lt;br /&gt;
== Internals (software) ==&lt;br /&gt;
The firmware is based on a [http://en.wikipedia.org/wiki/Forth_(programming_language) Forth] system which you can enter by sending the command &amp;lt;code&amp;gt;*b7#&amp;lt;/code&amp;gt; on its console stream (see above). For symmetry, there&#039;s also a Forth word called &amp;lt;code&amp;gt;*b7#&amp;lt;/code&amp;gt; which gets you back into the normal command mode. Entering the Forth console does not affect other streams or normal operation (as long as you don&#039;t mess anything up).&lt;br /&gt;
&lt;br /&gt;
There&#039;s a little script for logging into the lanbox Forth console in the [https://git.nurd.space/zmatt/lanbox-forth/tree/master lanbox-forth git repo].&lt;br /&gt;
&lt;br /&gt;
The LanBox-LCX Forth system is a fairly complete native-compiling Forth system with [[LanBox/ForthHelp|integrated help]] (not very complete unfortunately), assembler, disassembler, debugger, etc. Although the processor is 16-bit with segmented addressing, the Forth system is 32-bit with flat addressing for convenience. Several key routines of the firmware are written in assembly for performance.&lt;br /&gt;
&lt;br /&gt;
The firmware has several callback hooks (set to nop by default) to allow custom code to be run at various relevant moments:&lt;br /&gt;
&lt;br /&gt;
 &#039; nop VALUE &#039;StartTick    \ called in &amp;quot;start&amp;quot; after initialization, before the frame timer is started&lt;br /&gt;
 &#039; nop VALUE &#039;StopTick     \ called in &amp;quot;stop&amp;quot; after frame timer has halted but before any cleanup&lt;br /&gt;
 &#039; nop VALUE &#039;PreMixTick   \ called for every dmx frame before the sequence-fade-mix loop&lt;br /&gt;
 &#039; nop VALUE &#039;PostMixTick  \ called after mixer buffer is updated but before postprocessing&lt;br /&gt;
&lt;br /&gt;
It&#039;s also quite easy to patch dispatch tables to hook custom commands on e.g. MIDI messages.&lt;br /&gt;
&lt;br /&gt;
With some care you can directly manipulate internal buffers and structures (e.g. in &#039;PostMixTick you can manipulate the updated mixer buffer before anything else gets to see it), and many serial commands also have an equivalent high-level Forth word, for example:&lt;br /&gt;
&lt;br /&gt;
 ( 44 ) EnConfigure  ( layerID destlayerID -- ok? )&lt;br /&gt;
 ( 44 ) EnConfigureWithOptions  ( layerID destlayerID newlayerID flags cuelist cuestep -- ok? )&lt;br /&gt;
 ( 56 ) EnGo  ( layerID cuelist cuestep -- ok? )&lt;br /&gt;
 ( 57 ) EnClear  ( layerID -- ok? )&lt;br /&gt;
 ( 73 ) EnNextCue  ( layerID -- ok? )&lt;br /&gt;
&lt;br /&gt;
== Patchwork ==&lt;br /&gt;
Style convention: &amp;lt;span style=&amp;quot;color: #090; font-weight: bold;&amp;quot;&amp;gt;bold green&amp;lt;/span&amp;gt; indicates command input, output prompt is &amp;lt;span style=&amp;quot;color: #33c; font-weight: bold;&amp;quot;&amp;gt;blue&amp;lt;/span&amp;gt;, remaining output unstyled (except highlighting for emphasis).&lt;br /&gt;
&lt;br /&gt;
Firmware has been upgraded to latest version. This has been done via TCP, hence the console is now available via TCP port 778. The first time you [https://git.nurd.space/zmatt/lanbox-forth/blob/master/console.sh connect] to it (after boot) you&#039;ll get the buffered startup message thrown at you. Use the LC command &amp;lt;span style=&amp;quot;color: #090; font-weight: bold;&amp;quot;&amp;gt;*b7#&amp;lt;/span&amp;gt; to switch to Forth mode: as usual for LC commands, this is not echoed back but acknowledged with a &amp;lt;span style=&amp;quot;color: #33c; font-weight: bold;&amp;quot;&amp;gt;&amp;amp;gt;&amp;lt;/span&amp;gt;.&lt;br /&gt;
 &lt;br /&gt;
 LanBox-LCX system built Jun 26 2007 09:01:44&lt;br /&gt;
 --------------------------------------------&lt;br /&gt;
 &lt;br /&gt;
 &amp;lt;span style=&amp;quot;color: #090; font-weight: bold;&amp;quot;&amp;gt;*b7#&amp;lt;/span&amp;gt;&amp;lt;span style=&amp;quot;color: #33c; font-weight: bold;&amp;quot;&amp;gt;&amp;amp;gt;&amp;lt;/span&amp;gt;&lt;br /&gt;
Once in Forth mode, commands will be echoed. Press enter to see Forth&#039;s standard &amp;lt;span style=&amp;quot;color: #33c; font-weight: bold;&amp;quot;&amp;gt;ok&amp;lt;/span&amp;gt; prompt:&lt;br /&gt;
 &amp;lt;span style=&amp;quot;color: #090; font-weight: bold;&amp;quot;&amp;gt;*b7#&amp;lt;/span&amp;gt;&amp;lt;span style=&amp;quot;color: #33c; font-weight: bold;&amp;quot;&amp;gt;&amp;amp;gt;&amp;lt;/span&amp;gt; &amp;lt;span style=&amp;quot;color: #33c; font-weight: bold;&amp;quot;&amp;gt;ok&amp;lt;/span&amp;gt;&lt;br /&gt;
The console is not aware of disconnect/connect and will remain in whatever state it was left in.&lt;br /&gt;
&lt;br /&gt;
The bootloader settings have been changed to disable the CRC-verification of the firmware. This allows hassle-free customization of the firmware. This was done with the following Forth command:&lt;br /&gt;
 &amp;lt;span style=&amp;quot;color: #090; font-weight: bold;&amp;quot;&amp;gt;mon&amp;quot; setsysparams 08 RAMsys 10000 210000 2A0000 *0&amp;lt;/span&amp;gt;&lt;br /&gt;
 &amp;lt;span style=&amp;quot;color: #33c; font-weight: bold;&amp;quot;&amp;gt;ok&amp;lt;/span&amp;gt;&lt;br /&gt;
If firmware is reuploaded via LCedit, this will need to be done again before doing any persistent code modification (using &amp;lt;span style=&amp;quot;color: #090; font-weight: bold;&amp;quot;&amp;gt;savecode&amp;lt;/span&amp;gt;), or the LanBox will refuse to boot due to CRC mismatch.&lt;br /&gt;
&lt;br /&gt;
=== More UDP, less spam ===&lt;br /&gt;
Objective: allow the udp-transmit capability of the LanBox to be used (for efficiently getting the current state of the lanbox, including e.g. its analog inputs) without spamming the whole network with broadcasts.&lt;br /&gt;
&lt;br /&gt;
The destination address for udp transmit turned out to be hardcoded to -1 (i.e. 255.255.255.255):&lt;br /&gt;
 &amp;lt;span style=&amp;quot;color: #090; font-weight: bold;&amp;quot;&amp;gt;see udptxpacket&amp;lt;/span&amp;gt;&lt;br /&gt;
 UdpTxPacket &lt;br /&gt;
 0884B8  DA 04 EA 1C               041CEA    CALLS          ROT &lt;br /&gt;
 0884BC  EC F3                     R3        PUSH&lt;br /&gt;
 0884BE  EC F2                     R2        PUSH&lt;br /&gt;
 0884C0  98 20           R0  [+]   R2        MOV&lt;br /&gt;
 0884C2  98 30           R0  [+]   R3        MOV&lt;br /&gt;
 0884C4  DA 08 94 34               083494    CALLS          UdpOutPort &lt;br /&gt;
 &amp;lt;span style=&amp;quot;background: #ff9;&amp;quot;&amp;gt;0884C8  DA 04 8A 3E               043E8A    CALLS          -1 &lt;br /&gt;
 &amp;lt;/span&amp;gt;0884CC  DA 08 5A 37               08375A    CALLS          UdpSock &lt;br /&gt;
 0884D0  88 30           R3        R0  [-]   MOV&lt;br /&gt;
 0884D2  88 20           R2        R0  [-]   MOV&lt;br /&gt;
 0884D4  FC F2                     R2        POP&lt;br /&gt;
 0884D6  FC F3                     R3        POP&lt;br /&gt;
 0884D8  DA 08 94 30               083094    CALLS          SOCK-UDP-WRITE &lt;br /&gt;
 0884DC  DA 04 C4 1B               041BC4    CALLS          DROP &lt;br /&gt;
 0884E0  DB 00                               RETS &amp;lt;span style=&amp;quot;color: #33c; font-weight: bold;&amp;quot;&amp;gt;ok&amp;lt;/span&amp;gt;&lt;br /&gt;
since calls use absolute addresses (with funny byteorder) this was easy to patch to use UdpInAddr instead (which is convenient for the purpose since it&#039;s already configurable via global settings). First, check its address:&lt;br /&gt;
 &amp;lt;span style=&amp;quot;color: #090; font-weight: bold;&amp;quot;&amp;gt;&#039; udpinaddr .hex&amp;lt;/span&amp;gt; 83590 &amp;lt;span style=&amp;quot;color: #33c; font-weight: bold;&amp;quot;&amp;gt;ok&amp;lt;/span&amp;gt;&lt;br /&gt;
Patch the instruction (again look closely at byte order):&lt;br /&gt;
 &amp;lt;span style=&amp;quot;color: #090; font-weight: bold;&amp;quot;&amp;gt;$359008DA $0884C8 !&amp;lt;/span&amp;gt; &amp;lt;span style=&amp;quot;color: #33c; font-weight: bold;&amp;quot;&amp;gt;ok&amp;lt;/span&amp;gt;&lt;br /&gt;
And finally check the results:&lt;br /&gt;
 &amp;lt;span style=&amp;quot;color: #090; font-weight: bold;&amp;quot;&amp;gt;see udptxpacket&amp;lt;/span&amp;gt;&lt;br /&gt;
 ...&lt;br /&gt;
 0884C4  DA 08 94 34               083494    CALLS          UdpOutPort &lt;br /&gt;
 &amp;lt;span style=&amp;quot;background: #ff9;&amp;quot;&amp;gt;0884C8  DA 08 90 35               083590    CALLS          UdpInAddr &lt;br /&gt;
 &amp;lt;/span&amp;gt;0884CC  DA 08 5A 37               08375A    CALLS          UdpSock &lt;br /&gt;
 ... &amp;lt;span style=&amp;quot;color: #33c; font-weight: bold;&amp;quot;&amp;gt;ok&amp;lt;/span&amp;gt;&lt;br /&gt;
w00t!&lt;br /&gt;
&lt;br /&gt;
After thorough testing (read: it didn&#039;t crash, so I&#039;m sure it&#039;ll work fine), it&#039;s time to save the work done:&lt;br /&gt;
&lt;br /&gt;
Stop the application (in retrospect, maybe it would have been a better idea to do that &#039;&#039;before&#039;&#039; doing live code-patching), save code to flash, and reboot:&lt;br /&gt;
 &amp;lt;span style=&amp;quot;color: #090; font-weight: bold;&amp;quot;&amp;gt;stop&amp;lt;/span&amp;gt; &amp;lt;span style=&amp;quot;color: #33c; font-weight: bold;&amp;quot;&amp;gt;ok&amp;lt;/span&amp;gt;&lt;br /&gt;
 &amp;lt;span style=&amp;quot;color: #090; font-weight: bold;&amp;quot;&amp;gt;savecode&amp;lt;/span&amp;gt; &amp;lt;span style=&amp;quot;color: #33c; font-weight: bold;&amp;quot;&amp;gt;ok&amp;lt;/span&amp;gt;&lt;br /&gt;
 &amp;lt;span style=&amp;quot;color: #090; font-weight: bold;&amp;quot;&amp;gt;reset&amp;lt;/span&amp;gt;   &amp;lt;span style=&amp;quot;color: #999;&amp;quot;&amp;gt;&#039;&#039;\ (connection gone)&amp;lt;/span&amp;gt;&lt;br /&gt;
NOTE: Using &amp;lt;span style=&amp;quot;color: #090; font-weight: bold;&amp;quot;&amp;gt;savecode&amp;lt;/span&amp;gt; while the application is still running &#039;&#039;will&#039;&#039; fuck up the firmware. (&#039;&#039;&#039;TODO&#039;&#039;&#039;: add recovery procedure for fucked-up firmware.)&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=10101</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=10101"/>
		<updated>2020-01-31T16:00:32Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: Undo revision 10100 by Zmatt (talk)&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Beaglebones.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated BeagleBones seek projects that can give their life meaning.&#039;&#039;&#039; ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do).&lt;br /&gt;
&lt;br /&gt;
Don&#039;t be afraid to play with them, or use one in a project! That&#039;s what they&#039;re for!&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Do you want a 14-channel 100 Msps logic analyzer? Just run [https://beaglelogic.readthedocs.io/en/latest/ BeagleLogic] on a BeagleBone!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
Also, check out my [https://github.com/mvduin/py-uio/#uio_pruss py-uio] project for directly working with the PRU subsystem (and various other peripherals) from python code. Poke me on IRC if you have questions.&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
There are currently several donated BeagleBone Black (rev C) boards with minor defects, donated by [[User:zmatt|my]] employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]:&lt;br /&gt;
* &amp;quot;boner&amp;quot;. Has 3.3V regulator patch, battery header soldered on, and shown running on battery at the top of the page. One I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
* &amp;quot;ham-015&amp;quot;. eMMC is dead.&lt;br /&gt;
* &amp;quot;[[bb-leds]]&amp;quot; (007357+1650). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;8m-094&amp;quot;. eMMC is dead. Has 3.3V regulator patch, battery header soldered on.&lt;br /&gt;
* &amp;quot;licht-gebakken&amp;quot;. It&#039;s perfectly fine. No, really, I haven&#039;t noticed any problems with it.&lt;br /&gt;
* &amp;quot;[[Not-A-Phone|not-a-phone]]&amp;quot;. Idiot customer connected a phone line to the Ethernet port. PHY still works &#039;&#039;mostly&#039;&#039;, but link detection is wonky. Ethernet works if connected at power on, but hotplugging requires a tiny script (which has been installed) that periodically resets the PHY whenever network is down.&lt;br /&gt;
* &amp;quot;dead-pin-16&amp;quot;. BeagleBone appears to have a production fault: cpu pin 16 (GPIO 1.16) appears to be internally shorted to 3.3V, and attempting to drive it low results in more than 100 mA of current. It has been disconnected from P9.15 by desoldering R160, and P9.15 remains usable thanks to its connection to cpu pin 34 (GPIO 2.00).&lt;br /&gt;
* &amp;quot;ham-059&amp;quot; (007270+1650). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* unlabeled (005857+1651). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;julia&amp;quot; (XAN004945). eMMC is dead. Has 3.3V regulator patch.&lt;br /&gt;
* &amp;quot;8c-132&amp;quot; (005670+1634). eMMC is dead.&lt;br /&gt;
* unlabeled (000010+1720). eMMC is dead.&lt;br /&gt;
* unlabeled (002474+1823). unclear ethernet issues. worked fine on one switch, consistently didn&#039;t work on another switch.&lt;br /&gt;
* &amp;quot;8c-399&amp;quot; (003876+1823). expansion header pins P8.07-10 are solder blobbed together.&lt;br /&gt;
* unlabeled (004847+1850). sd card slot does not work.&lt;br /&gt;
Soon to be added:&lt;br /&gt;
* &amp;quot;8c-186&amp;quot; (004671+1729). No obvious problem, but has probably been exposed to ESD.&lt;br /&gt;
* &amp;quot;8c-421&amp;quot; (006510+1823). No obvious problem, but has probably been exposed to ESD.&lt;br /&gt;
* &amp;quot;8c-599&amp;quot; (000385+1838). No obvious problem, but has probably been exposed to ESD.&lt;br /&gt;
&lt;br /&gt;
The BeagleBones with dead (worn out) eMMC need to boot from μSD card instead, or netboot if you&#039;re feeling adventurous.&lt;br /&gt;
&lt;br /&gt;
When the USB mini-B port is missing, the beaglebone can be powered via 5V barrel jack or via expansion header P9 (connect P9.01 and/or P9.02 to ground, connect P9.05 and/or P9.06 to 5V)&lt;br /&gt;
&lt;br /&gt;
The &amp;quot;3.3V regulator patch&amp;quot; means the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; &amp;lt;strike&amp;gt;in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft&amp;lt;/strike&amp;gt; maybe still somewhere in the space.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed with a basic firmware image (debian stretch with customizations). You can reach it with &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777. There is a README file in the home directory, I might also put more details here if I get less lazy.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host port inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Supports Wayland but not X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=10100</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=10100"/>
		<updated>2020-01-31T15:58:38Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Peripherals */ 3*2+3+4-1 = 12, not 13&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Beaglebones.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated BeagleBones seek projects that can give their life meaning.&#039;&#039;&#039; ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do).&lt;br /&gt;
&lt;br /&gt;
Don&#039;t be afraid to play with them, or use one in a project! That&#039;s what they&#039;re for!&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Do you want a 14-channel 100 Msps logic analyzer? Just run [https://beaglelogic.readthedocs.io/en/latest/ BeagleLogic] on a BeagleBone!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
Also, check out my [https://github.com/mvduin/py-uio/#uio_pruss py-uio] project for directly working with the PRU subsystem (and various other peripherals) from python code. Poke me on IRC if you have questions.&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
There are currently several donated BeagleBone Black (rev C) boards with minor defects, donated by [[User:zmatt|my]] employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]:&lt;br /&gt;
* &amp;quot;boner&amp;quot;. Has 3.3V regulator patch, battery header soldered on, and shown running on battery at the top of the page. One I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
* &amp;quot;ham-015&amp;quot;. eMMC is dead.&lt;br /&gt;
* &amp;quot;[[bb-leds]]&amp;quot; (007357+1650). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;8m-094&amp;quot;. eMMC is dead. Has 3.3V regulator patch, battery header soldered on.&lt;br /&gt;
* &amp;quot;licht-gebakken&amp;quot;. It&#039;s perfectly fine. No, really, I haven&#039;t noticed any problems with it.&lt;br /&gt;
* &amp;quot;[[Not-A-Phone|not-a-phone]]&amp;quot;. Idiot customer connected a phone line to the Ethernet port. PHY still works &#039;&#039;mostly&#039;&#039;, but link detection is wonky. Ethernet works if connected at power on, but hotplugging requires a tiny script (which has been installed) that periodically resets the PHY whenever network is down.&lt;br /&gt;
* &amp;quot;dead-pin-16&amp;quot;. BeagleBone appears to have a production fault: cpu pin 16 (GPIO 1.16) appears to be internally shorted to 3.3V, and attempting to drive it low results in more than 100 mA of current. It has been disconnected from P9.15 by desoldering R160, and P9.15 remains usable thanks to its connection to cpu pin 34 (GPIO 2.00).&lt;br /&gt;
* &amp;quot;ham-059&amp;quot; (007270+1650). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* unlabeled (005857+1651). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;julia&amp;quot; (XAN004945). eMMC is dead. Has 3.3V regulator patch.&lt;br /&gt;
* &amp;quot;8c-132&amp;quot; (005670+1634). eMMC is dead.&lt;br /&gt;
* unlabeled (000010+1720). eMMC is dead.&lt;br /&gt;
* unlabeled (002474+1823). unclear ethernet issues. worked fine on one switch, consistently didn&#039;t work on another switch.&lt;br /&gt;
* &amp;quot;8c-399&amp;quot; (003876+1823). expansion header pins P8.07-10 are solder blobbed together.&lt;br /&gt;
* unlabeled (004847+1850). sd card slot does not work.&lt;br /&gt;
Soon to be added:&lt;br /&gt;
* &amp;quot;8c-186&amp;quot; (004671+1729). No obvious problem, but has probably been exposed to ESD.&lt;br /&gt;
* &amp;quot;8c-421&amp;quot; (006510+1823). No obvious problem, but has probably been exposed to ESD.&lt;br /&gt;
* &amp;quot;8c-599&amp;quot; (000385+1838). No obvious problem, but has probably been exposed to ESD.&lt;br /&gt;
&lt;br /&gt;
The BeagleBones with dead (worn out) eMMC need to boot from μSD card instead, or netboot if you&#039;re feeling adventurous.&lt;br /&gt;
&lt;br /&gt;
When the USB mini-B port is missing, the beaglebone can be powered via 5V barrel jack or via expansion header P9 (connect P9.01 and/or P9.02 to ground, connect P9.05 and/or P9.06 to 5V)&lt;br /&gt;
&lt;br /&gt;
The &amp;quot;3.3V regulator patch&amp;quot; means the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; &amp;lt;strike&amp;gt;in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft&amp;lt;/strike&amp;gt; maybe still somewhere in the space.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed with a basic firmware image (debian stretch with customizations). You can reach it with &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777. There is a README file in the home directory, I might also put more details here if I get less lazy.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host port inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Supports Wayland but not X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 12 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=10099</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=10099"/>
		<updated>2020-01-31T15:41:47Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Description */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Beaglebones.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated BeagleBones seek projects that can give their life meaning.&#039;&#039;&#039; ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do).&lt;br /&gt;
&lt;br /&gt;
Don&#039;t be afraid to play with them, or use one in a project! That&#039;s what they&#039;re for!&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Do you want a 14-channel 100 Msps logic analyzer? Just run [https://beaglelogic.readthedocs.io/en/latest/ BeagleLogic] on a BeagleBone!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
Also, check out my [https://github.com/mvduin/py-uio/#uio_pruss py-uio] project for directly working with the PRU subsystem (and various other peripherals) from python code. Poke me on IRC if you have questions.&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
There are currently several donated BeagleBone Black (rev C) boards with minor defects, donated by [[User:zmatt|my]] employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]:&lt;br /&gt;
* &amp;quot;boner&amp;quot;. Has 3.3V regulator patch, battery header soldered on, and shown running on battery at the top of the page. One I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
* &amp;quot;ham-015&amp;quot;. eMMC is dead.&lt;br /&gt;
* &amp;quot;[[bb-leds]]&amp;quot; (007357+1650). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;8m-094&amp;quot;. eMMC is dead. Has 3.3V regulator patch, battery header soldered on.&lt;br /&gt;
* &amp;quot;licht-gebakken&amp;quot;. It&#039;s perfectly fine. No, really, I haven&#039;t noticed any problems with it.&lt;br /&gt;
* &amp;quot;[[Not-A-Phone|not-a-phone]]&amp;quot;. Idiot customer connected a phone line to the Ethernet port. PHY still works &#039;&#039;mostly&#039;&#039;, but link detection is wonky. Ethernet works if connected at power on, but hotplugging requires a tiny script (which has been installed) that periodically resets the PHY whenever network is down.&lt;br /&gt;
* &amp;quot;dead-pin-16&amp;quot;. BeagleBone appears to have a production fault: cpu pin 16 (GPIO 1.16) appears to be internally shorted to 3.3V, and attempting to drive it low results in more than 100 mA of current. It has been disconnected from P9.15 by desoldering R160, and P9.15 remains usable thanks to its connection to cpu pin 34 (GPIO 2.00).&lt;br /&gt;
* &amp;quot;ham-059&amp;quot; (007270+1650). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* unlabeled (005857+1651). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;julia&amp;quot; (XAN004945). eMMC is dead. Has 3.3V regulator patch.&lt;br /&gt;
* &amp;quot;8c-132&amp;quot; (005670+1634). eMMC is dead.&lt;br /&gt;
* unlabeled (000010+1720). eMMC is dead.&lt;br /&gt;
* unlabeled (002474+1823). unclear ethernet issues. worked fine on one switch, consistently didn&#039;t work on another switch.&lt;br /&gt;
* &amp;quot;8c-399&amp;quot; (003876+1823). expansion header pins P8.07-10 are solder blobbed together.&lt;br /&gt;
* unlabeled (004847+1850). sd card slot does not work.&lt;br /&gt;
Soon to be added:&lt;br /&gt;
* &amp;quot;8c-186&amp;quot; (004671+1729). No obvious problem, but has probably been exposed to ESD.&lt;br /&gt;
* &amp;quot;8c-421&amp;quot; (006510+1823). No obvious problem, but has probably been exposed to ESD.&lt;br /&gt;
* &amp;quot;8c-599&amp;quot; (000385+1838). No obvious problem, but has probably been exposed to ESD.&lt;br /&gt;
&lt;br /&gt;
The BeagleBones with dead (worn out) eMMC need to boot from μSD card instead, or netboot if you&#039;re feeling adventurous.&lt;br /&gt;
&lt;br /&gt;
When the USB mini-B port is missing, the beaglebone can be powered via 5V barrel jack or via expansion header P9 (connect P9.01 and/or P9.02 to ground, connect P9.05 and/or P9.06 to 5V)&lt;br /&gt;
&lt;br /&gt;
The &amp;quot;3.3V regulator patch&amp;quot; means the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; &amp;lt;strike&amp;gt;in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft&amp;lt;/strike&amp;gt; maybe still somewhere in the space.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed with a basic firmware image (debian stretch with customizations). You can reach it with &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777. There is a README file in the home directory, I might also put more details here if I get less lazy.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host port inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Supports Wayland but not X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=9999</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=9999"/>
		<updated>2020-01-02T14:39:23Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Description */ label of ham-050 changed to bb-leds (its hostname)&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Beaglebones.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated BeagleBones seek projects that can give their life meaning.&#039;&#039;&#039; ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do).&lt;br /&gt;
&lt;br /&gt;
Don&#039;t be afraid to play with them, or use one in a project! That&#039;s what they&#039;re for!&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Do you want a 14-channel 100 Msps logic analyzer? Just run [https://beaglelogic.readthedocs.io/en/latest/ BeagleLogic] on a BeagleBone!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
Also, check out my [https://github.com/mvduin/py-uio/#uio_pruss py-uio] project for directly working with the PRU subsystem (and various other peripherals) from python code. Poke me on IRC if you have questions.&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
There are currently several donated BeagleBone Black (rev C) boards with minor defects, donated by [[User:zmatt|my]] employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]:&lt;br /&gt;
* &amp;quot;boner&amp;quot;. Has 3.3V regulator patch, battery header soldered on, and shown running on battery at the top of the page. One I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
* &amp;quot;ham-015&amp;quot;. eMMC is dead.&lt;br /&gt;
* &amp;quot;[[bb-leds]]&amp;quot; (007357+1650). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;8m-094&amp;quot;. eMMC is dead. Has 3.3V regulator patch, battery header soldered on.&lt;br /&gt;
* &amp;quot;licht-gebakken&amp;quot;. It&#039;s perfectly fine. No, really, I haven&#039;t noticed any problems with it.&lt;br /&gt;
* &amp;quot;[[Not-A-Phone|not-a-phone]]&amp;quot;. Idiot customer connected a phone line to the Ethernet port. PHY still works &#039;&#039;mostly&#039;&#039;, but link detection is wonky. Ethernet works if connected at power on, but hotplugging requires a tiny script (which has been installed) that periodically resets the PHY whenever network is down.&lt;br /&gt;
* &amp;quot;dead-pin-16&amp;quot;. BeagleBone appears to have a production fault: cpu pin 16 (GPIO 1.16) appears to be internally shorted to 3.3V, and attempting to drive it low results in more than 100 mA of current. It has been disconnected from P9.15 by desoldering R160, and P9.15 remains usable thanks to its connection to cpu pin 34 (GPIO 2.00).&lt;br /&gt;
* &amp;quot;ham-059&amp;quot; (007270+1650). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* unlabeled (005857+1651). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;julia&amp;quot; (XAN004945). eMMC is dead. Has 3.3V regulator patch.&lt;br /&gt;
* &amp;quot;8c-132&amp;quot; (005670+1634). eMMC is dead.&lt;br /&gt;
* unlabeled (000010+1720). eMMC is dead.&lt;br /&gt;
* unlabeled (002474+1823). unclear ethernet issues. worked fine on one switch, consistently didn&#039;t work on another switch.&lt;br /&gt;
* &amp;quot;8c-399&amp;quot; (003876+1823). expansion header pins P8.07-10 are solder blobbed together.&lt;br /&gt;
* unlabeled (004847+1850). sd card slot does not work.&lt;br /&gt;
&lt;br /&gt;
The BeagleBones with dead (worn out) eMMC need to boot from μSD card instead, or netboot if you&#039;re feeling adventurous.&lt;br /&gt;
&lt;br /&gt;
When the USB mini-B port is missing, the beaglebone can be powered via 5V barrel jack or via expansion header P9 (connect P9.01 and/or P9.02 to ground, connect P9.05 and/or P9.06 to 5V)&lt;br /&gt;
&lt;br /&gt;
The &amp;quot;3.3V regulator patch&amp;quot; means the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; &amp;lt;strike&amp;gt;in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft&amp;lt;/strike&amp;gt; maybe still somewhere in the space.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed with a basic firmware image (debian stretch with customizations). You can reach it with &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777. There is a README file in the home directory, I might also put more details here if I get less lazy.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host port inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Supports Wayland but not X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=Ham-050&amp;diff=9998</id>
		<title>Ham-050</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=Ham-050&amp;diff=9998"/>
		<updated>2020-01-02T14:38:16Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: Zmatt moved page Ham-050 to Bb-leds: label changed to match hostname&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;#REDIRECT [[Bb-leds]]&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=Bb-leds&amp;diff=9997</id>
		<title>Bb-leds</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=Bb-leds&amp;diff=9997"/>
		<updated>2020-01-02T14:38:16Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: Zmatt moved page Ham-050 to Bb-leds: label changed to match hostname&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=Ham-050&lt;br /&gt;
|Tool=No&lt;br /&gt;
}}&lt;br /&gt;
Being connected to led tickers donated from ]LAG( (2* 3 rows)&lt;br /&gt;
Has pro-mini attached for use as &#039;level converter&#039;.&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=9991</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=9991"/>
		<updated>2020-01-01T02:13:25Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Description */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Beaglebones.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated BeagleBones seek projects that can give their life meaning.&#039;&#039;&#039; ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do).&lt;br /&gt;
&lt;br /&gt;
Don&#039;t be afraid to play with them, or use one in a project! That&#039;s what they&#039;re for!&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Do you want a 14-channel 100 Msps logic analyzer? Just run [https://beaglelogic.readthedocs.io/en/latest/ BeagleLogic] on a BeagleBone!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
Also, check out my [https://github.com/mvduin/py-uio/#uio_pruss py-uio] project for directly working with the PRU subsystem (and various other peripherals) from python code. Poke me on IRC if you have questions.&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
There are currently several donated BeagleBone Black (rev C) boards with minor defects, donated by [[User:zmatt|my]] employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]:&lt;br /&gt;
* &amp;quot;boner&amp;quot;. Has 3.3V regulator patch, battery header soldered on, and shown running on battery at the top of the page. One I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
* &amp;quot;ham-015&amp;quot;. eMMC is dead.&lt;br /&gt;
* &amp;quot;ham-050&amp;quot;. eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;8m-094&amp;quot;. eMMC is dead. Has 3.3V regulator patch, battery header soldered on.&lt;br /&gt;
* &amp;quot;licht-gebakken&amp;quot;. It&#039;s perfectly fine. No, really, I haven&#039;t noticed any problems with it.&lt;br /&gt;
* &amp;quot;[[Not-A-Phone|not-a-phone]]&amp;quot;. Idiot customer connected a phone line to the Ethernet port. PHY still works &#039;&#039;mostly&#039;&#039;, but link detection is wonky. Ethernet works if connected at power on, but hotplugging requires a tiny script (which has been installed) that periodically resets the PHY whenever network is down.&lt;br /&gt;
* &amp;quot;dead-pin-16&amp;quot;. BeagleBone appears to have a production fault: cpu pin 16 (GPIO 1.16) appears to be internally shorted to 3.3V, and attempting to drive it low results in more than 100 mA of current. It has been disconnected from P9.15 by desoldering R160, and P9.15 remains usable thanks to its connection to cpu pin 34 (GPIO 2.00).&lt;br /&gt;
* &amp;quot;ham-059&amp;quot; (007270+1650). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* unlabeled (005857+1651). eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;julia&amp;quot; (XAN004945). eMMC is dead. Has 3.3V regulator patch.&lt;br /&gt;
* &amp;quot;8c-132&amp;quot; (005670+1634). eMMC is dead.&lt;br /&gt;
* unlabeled (000010+1720). eMMC is dead.&lt;br /&gt;
* unlabeled (002474+1823). unclear ethernet issues. worked fine on one switch, consistently didn&#039;t work on another switch.&lt;br /&gt;
* &amp;quot;8c-399&amp;quot; (003876+1823). expansion header pins P8.07-10 are solder blobbed together.&lt;br /&gt;
* unlabeled (004847+1850). sd card slot does not work.&lt;br /&gt;
&lt;br /&gt;
The BeagleBones with dead (worn out) eMMC need to boot from μSD card instead, or netboot if you&#039;re feeling adventurous.&lt;br /&gt;
&lt;br /&gt;
When the USB mini-B port is missing, the beaglebone can be powered via 5V barrel jack or via expansion header P9 (connect P9.01 and/or P9.02 to ground, connect P9.05 and/or P9.06 to 5V)&lt;br /&gt;
&lt;br /&gt;
The &amp;quot;3.3V regulator patch&amp;quot; means the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; &amp;lt;strike&amp;gt;in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft&amp;lt;/strike&amp;gt; maybe still somewhere in the space.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed with a basic firmware image (debian stretch with customizations). You can reach it with &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777. There is a README file in the home directory, I might also put more details here if I get less lazy.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host port inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Supports Wayland but not X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=NurdInn_Neuzeleditie_2019&amp;diff=9481</id>
		<title>NurdInn Neuzeleditie 2019</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=NurdInn_Neuzeleditie_2019&amp;diff=9481"/>
		<updated>2019-06-16T02:35:32Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Who */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Event&lt;br /&gt;
|Name=NurdInn Neuzeleditie 2019&lt;br /&gt;
|Date=2019/07/12&lt;br /&gt;
|DateEnd=2019/07/14&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
= Who =&lt;br /&gt;
* buZz&lt;br /&gt;
* Boots&lt;br /&gt;
* Niz (herp and derp)&lt;br /&gt;
* dreamer (flurp and snurp)&lt;br /&gt;
* zmatt&lt;br /&gt;
&lt;br /&gt;
= Bürrel =&lt;br /&gt;
July 13th is also 103&#039;s [https://joriszwart.nl/burrel2019/uitnodiging.html Bürrel]. Who&#039;s going:&lt;br /&gt;
* Niz&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=CCCamp_2019&amp;diff=9447</id>
		<title>CCCamp 2019</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=CCCamp_2019&amp;diff=9447"/>
		<updated>2019-05-29T18:25:15Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Event&lt;br /&gt;
|Name=CCCamp 2019&lt;br /&gt;
|Date=2019/08/21&lt;br /&gt;
|DateEnd=2019/08/25&lt;br /&gt;
|Location=Zehdenick&lt;br /&gt;
}}&lt;br /&gt;
=who=&lt;br /&gt;
* dreamer&lt;br /&gt;
* buZz&lt;br /&gt;
* the0&lt;br /&gt;
* nooitaf&lt;br /&gt;
* pokon&lt;br /&gt;
* [[User:zmatt|zmatt]]&lt;br /&gt;
* ..&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=9063</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=9063"/>
		<updated>2018-12-31T01:03:28Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: update image&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Beaglebones.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated BeagleBones seek projects that can give their life meaning.&#039;&#039;&#039; ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do).&lt;br /&gt;
&lt;br /&gt;
Don&#039;t be afraid to play with them, or use one in a project! That&#039;s what they&#039;re for!&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Do you want a 14-channel 100 Msps logic analyzer? Just run [https://beaglelogic.readthedocs.io/en/latest/ BeagleLogic] on a BeagleBone!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
Also, check out my [https://github.com/mvduin/py-uio/#uio_pruss py-uio] project for directly working with the PRU subsystem (and various other peripherals) from python code. Poke me on IRC if you have questions.&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
There are currently several donated BeagleBone Black (rev C) boards with minor defects, donated by [[User:zmatt|my]] employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]:&lt;br /&gt;
* &amp;quot;boner&amp;quot;. Has 3.3V regulator patch, battery header soldered on, and shown running on battery at the top of the page. One I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
* &amp;quot;ham-015&amp;quot;. eMMC is dead.&lt;br /&gt;
* &amp;quot;ham-050&amp;quot;. eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;8m-094&amp;quot;. eMMC is dead. Has 3.3V regulator patch, battery header soldered on.&lt;br /&gt;
* &amp;quot;licht-gebakken&amp;quot;. It&#039;s perfectly fine. No, really, I haven&#039;t noticed any problems with it.&lt;br /&gt;
* &amp;quot;[[Not-A-Phone|not-a-phone]]&amp;quot;. Idiot customer connected a phone line to the Ethernet port. PHY still works &#039;&#039;mostly&#039;&#039;, but link detection is wonky. Ethernet works if connected at power on, but hotplugging requires a tiny script (which has been installed) that periodically resets the PHY whenever network is down.&lt;br /&gt;
* &amp;quot;dead-pin-16&amp;quot;. BeagleBone appears to have a production fault: cpu pin 16 (GPIO 1.16) appears to be internally shorted to 3.3V, and attempting to drive it low results in more than 100 mA of current. It has been disconnected from P9.15 by desoldering R160, and P9.15 remains usable thanks to its connection to cpu pin 34 (GPIO 2.00).&lt;br /&gt;
&lt;br /&gt;
The BeagleBones with dead (worn out) eMMC need to boot from μSD card instead, or netboot if you&#039;re feeling adventurous.&lt;br /&gt;
&lt;br /&gt;
The &amp;quot;3.3V regulator patch&amp;quot; means the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; &amp;lt;strike&amp;gt;in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft&amp;lt;/strike&amp;gt; maybe still somewhere in the space.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed with a basic firmware image (debian stretch with customizations). You can reach it with &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777. There is a README file in the home directory, I might also put more details here if I get less lazy.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host port inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Supports Wayland but not X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=File:Beaglebones.jpg&amp;diff=9062</id>
		<title>File:Beaglebones.jpg</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=File:Beaglebones.jpg&amp;diff=9062"/>
		<updated>2018-12-31T01:02:42Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: Beaglebones in inventory&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;Beaglebones in inventory&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=Nurd%26Nieuw_2019_VIP_edition&amp;diff=9061</id>
		<title>Nurd&amp;Nieuw 2019 VIP edition</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=Nurd%26Nieuw_2019_VIP_edition&amp;diff=9061"/>
		<updated>2018-12-29T19:14:30Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Event&lt;br /&gt;
|Name=Nurd&amp;amp;Nieuw 2019 VIP edition&lt;br /&gt;
|Date=2018/12/28&lt;br /&gt;
|DateEnd=2019/01/02&lt;br /&gt;
|Location=NURDspace&lt;br /&gt;
|Contact=IRC&lt;br /&gt;
}}&lt;br /&gt;
Check it out! Come and have a blast @ NURDspace during the Nurd&amp;amp;Nieuw Very Important Party 201[89] edition.&lt;br /&gt;
&lt;br /&gt;
Add yourself to the list below if you are a Very Important Person that needs to be at this party:&lt;br /&gt;
* pochenk&lt;br /&gt;
* SpiderWebz&lt;br /&gt;
* [[User:R3boot|R3boot]] ([[User talk:R3boot|talk]]) (whisky mee!!)&lt;br /&gt;
* [[User:Psy0rz|psy0rz]]&lt;br /&gt;
* buZz&lt;br /&gt;
* bavrogar &amp;amp; gloin&lt;br /&gt;
* niz&lt;br /&gt;
* albundy &amp;amp; manon &amp;amp; mayamisschien&lt;br /&gt;
* [[User:Dvanzuijlekom|dvanzuijlekom]] Komt VIPs kidnappen voor [https://flic.kr/s/aHskhj74xo Shoot ALL the Hackers!]&lt;br /&gt;
* drwhax misschien :)&lt;br /&gt;
* aczid \o/&lt;br /&gt;
* stef&lt;br /&gt;
* dreamer&lt;br /&gt;
* vierla&lt;br /&gt;
* anus&lt;br /&gt;
* invict&lt;br /&gt;
* [[User:zmatt|zmatt]]&lt;br /&gt;
*&lt;br /&gt;
* jij?&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=Not-A-Phone&amp;diff=8877</id>
		<title>Not-A-Phone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=Not-A-Phone&amp;diff=8877"/>
		<updated>2018-08-14T11:39:46Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=Not-A-Phone (it&#039;s a kassa)&lt;br /&gt;
|Skills=Electronics, Python, money,&lt;br /&gt;
|Status=Getting parts&lt;br /&gt;
|Niche=Hardware&lt;br /&gt;
|Purpose=Electronics, fun, world domination&lt;br /&gt;
|Tool=No&lt;br /&gt;
|Location=Bar&lt;br /&gt;
|Category=General&lt;br /&gt;
}}&lt;br /&gt;
We gutted the old Volkshuis cash-register.&lt;br /&gt;
&lt;br /&gt;
The money-tray is in use at the bar, but the top half with buttons and screens needs a brain!&lt;br /&gt;
&lt;br /&gt;
One of the donated [[BeagleBone]]s (called: Not-A-Phone) is serving this purpose, hence the name.&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
==Done==&lt;br /&gt;
* gut old electronics&lt;br /&gt;
* attach keyboard/buttons to BBB with custom header&lt;br /&gt;
* PRU-code to read pins&lt;br /&gt;
* python code to read PRU interrupts&lt;br /&gt;
&lt;br /&gt;
==Todo==&lt;br /&gt;
* get 2nd hd44780&lt;br /&gt;
* get 2x i2c-port-expanders for the hd44780&lt;br /&gt;
* attach barcode scanner&lt;br /&gt;
* code some sort of interactive cash-register-system-something&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=8861</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=8861"/>
		<updated>2018-08-11T17:44:07Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Description */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Bbb-zmattified.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated BeagleBones seek projects that can give their life meaning.&#039;&#039;&#039; ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do).&lt;br /&gt;
&lt;br /&gt;
Don&#039;t be afraid to play with them, or use one in a project! That&#039;s what they&#039;re for!&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Do you want a 14-channel 100 Msps logic analyzer? Just run [https://beaglelogic.readthedocs.io/en/latest/ BeagleLogic] on a BeagleBone!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
Also, check out my [https://github.com/mvduin/py-uio/#uio_pruss py-uio] project for directly working with the PRU subsystem (and various other peripherals) from python code. Poke me on IRC if you have questions.&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
There are currently several donated BeagleBone Black (rev C) boards with minor defects, donated by [[User:zmatt|my]] employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]:&lt;br /&gt;
* &amp;quot;boner&amp;quot;. Has 3.3V regulator patch, battery header soldered on, and shown running on battery at the top of the page. One I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
* &amp;quot;ham-015&amp;quot;. eMMC is dead.&lt;br /&gt;
* &amp;quot;ham-050&amp;quot;. eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;8m-094&amp;quot;. eMMC is dead. Has 3.3V regulator patch, battery header soldered on.&lt;br /&gt;
* &amp;quot;licht-gebakken&amp;quot;. It&#039;s perfectly fine. No, really, I haven&#039;t noticed any problems with it.&lt;br /&gt;
* &amp;quot;not-a-phone&amp;quot;. Idiot customer connected a phone line to the Ethernet port. PHY still works &#039;&#039;mostly&#039;&#039;, but link detection is wonky. Ethernet works if connected at power on, but hotplugging requires a tiny script (which has been installed) that periodically resets the PHY whenever network is down.&lt;br /&gt;
* &amp;quot;dead-pin-16&amp;quot;. BeagleBone appears to have a production fault: cpu pin 16 (GPIO 1.16) appears to be internally shorted to 3.3V, and attempting to drive it low results in more than 100 mA of current. It has been disconnected from P9.15 by desoldering R160, and P9.15 remains usable thanks to its connection to cpu pin 34 (GPIO 2.00).&lt;br /&gt;
&lt;br /&gt;
The BeagleBones with dead (worn out) eMMC need to boot from μSD card instead, or netboot if you&#039;re feeling adventurous.&lt;br /&gt;
&lt;br /&gt;
The &amp;quot;3.3V regulator patch&amp;quot; means the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; &amp;lt;strike&amp;gt;in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft&amp;lt;/strike&amp;gt; maybe still somewhere in the space.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed with a basic firmware image (debian stretch with customizations). You can reach it with &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777. There is a README file in the home directory, I might also put more details here if I get less lazy.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host port inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Supports Wayland but not X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=8725</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=8725"/>
		<updated>2018-06-25T15:16:09Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Description */ add two more beaglebones to list&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Bbb-zmattified.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated BeagleBones seek projects that can give their life meaning.&#039;&#039;&#039; ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do).&lt;br /&gt;
&lt;br /&gt;
Don&#039;t be afraid to play with them, or use one in a project! That&#039;s what they&#039;re for!&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Do you want a 14-channel 100 Msps logic analyzer? Just run [https://beaglelogic.readthedocs.io/en/latest/ BeagleLogic] on a BeagleBone!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
Also, check out my [https://github.com/mvduin/py-uio/#uio_pruss py-uio] project for directly working with the PRU subsystem (and various other peripherals) from python code. Poke me on IRC if you have questions.&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
There are currently several donated BeagleBone Black (rev C) boards with minor defects, donated by [[User:zmatt|my]] employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]:&lt;br /&gt;
* &amp;quot;boner&amp;quot;. Has 3.3V regulator patch, battery header soldered on, and shown running on battery at the top of the page. One I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
* &amp;quot;ham-015&amp;quot;. eMMC is dead.&lt;br /&gt;
* &amp;quot;ham-050&amp;quot;. eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;8m-094&amp;quot;. eMMC is dead. Has 3.3V regulator patch, battery header soldered on.&lt;br /&gt;
* &amp;quot;licht-gebakken&amp;quot;. It&#039;s perfectly fine. No, really, I haven&#039;t noticed any problems with it.&lt;br /&gt;
More will arrive at the space at the next opportunity:&lt;br /&gt;
* &amp;quot;not-a-phone&amp;quot;. Idiot customer connected a phone line to the Ethernet port. PHY still works &#039;&#039;mostly&#039;&#039;, but link detection is wonky. Ethernet works if connected at power on, but hotplugging requires a tiny script that periodically resets the PHY whenever network is down.&lt;br /&gt;
* &amp;quot;dead-pin-16&amp;quot;. BeagleBone appears to have a production fault: cpu pin 16 (GPIO 1.16) appears to be internally shorted to 3.3V, and attempting to drive it low results in more than 100 mA of current. It has been disconnected from P9.15 by desoldering R160, and P9.15 remains usable thanks to its connection to cpu pin 34 (GPIO 2.00).&lt;br /&gt;
&lt;br /&gt;
The BeagleBones with dead (worn out) eMMC need to boot from μSD card instead, or netboot if you&#039;re feeling adventurous.&lt;br /&gt;
&lt;br /&gt;
The &amp;quot;3.3V regulator patch&amp;quot; means the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; &amp;lt;strike&amp;gt;in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft&amp;lt;/strike&amp;gt; maybe still somewhere in the space.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed with a basic firmware image (debian stretch with customizations). You can reach it with &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777. There is a README file in the home directory, I might also put more details here if I get less lazy.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host port inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Supports Wayland but not X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=8724</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=8724"/>
		<updated>2018-06-25T14:53:04Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* TL;DR */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Bbb-zmattified.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated BeagleBones seek projects that can give their life meaning.&#039;&#039;&#039; ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do).&lt;br /&gt;
&lt;br /&gt;
Don&#039;t be afraid to play with them, or use one in a project! That&#039;s what they&#039;re for!&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Do you want a 14-channel 100 Msps logic analyzer? Just run [https://beaglelogic.readthedocs.io/en/latest/ BeagleLogic] on a BeagleBone!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
Also, check out my [https://github.com/mvduin/py-uio/#uio_pruss py-uio] project for directly working with the PRU subsystem (and various other peripherals) from python code. Poke me on IRC if you have questions.&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
There are currently several donated BeagleBone Black (rev C) boards with minor defects, donated by [[User:zmatt|my]] employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]:&lt;br /&gt;
* &amp;quot;boner&amp;quot;. Has 3.3V regulator patch, battery header soldered on, and shown running on battery at the top of the page. One I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
* &amp;quot;ham-015&amp;quot;. eMMC is dead.&lt;br /&gt;
* &amp;quot;ham-050&amp;quot;. eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;8m-094&amp;quot;. eMMC is dead. Has 3.3V regulator patch, battery header soldered on.&lt;br /&gt;
* &amp;quot;licht-gebakken&amp;quot;. It&#039;s perfectly fine. No, really, I haven&#039;t noticed any problems with it.&lt;br /&gt;
&lt;br /&gt;
The BeagleBones with dead (worn out) eMMC need to boot from μSD card instead, or netboot if you&#039;re feeling adventurous.&lt;br /&gt;
&lt;br /&gt;
The &amp;quot;3.3V regulator patch&amp;quot; means the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; &amp;lt;strike&amp;gt;in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft&amp;lt;/strike&amp;gt; maybe still somewhere in the space.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed with a basic firmware image (debian stretch with customizations). You can reach it with &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777. There is a README file in the home directory, I might also put more details here if I get less lazy.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host port inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Supports Wayland but not X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=8557</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=8557"/>
		<updated>2018-05-06T14:37:58Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Description */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Bbb-zmattified.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated BeagleBones seek projects that can give their life meaning.&#039;&#039;&#039; ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do). Don&#039;t be afraid to play with it!&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Do you want a 14-channel 100 Msps logic analyzer? Just run [https://beaglelogic.readthedocs.io/en/latest/ BeagleLogic] on a BeagleBone!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
Also, check out my [https://github.com/mvduin/py-uio/#uio_pruss py-uio] project for directly working with the PRU subsystem (and various other peripherals) from python code. Poke me on IRC if you have questions.&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
There are currently several donated BeagleBone Black (rev C) boards with minor defects, donated by [[User:zmatt|my]] employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]:&lt;br /&gt;
* &amp;quot;boner&amp;quot;. Has 3.3V regulator patch, battery header soldered on, and shown running on battery at the top of the page. One I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
* &amp;quot;ham-015&amp;quot;. eMMC is dead.&lt;br /&gt;
* &amp;quot;ham-050&amp;quot;. eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;8m-094&amp;quot;. eMMC is dead. Has 3.3V regulator patch, battery header soldered on.&lt;br /&gt;
* &amp;quot;licht-gebakken&amp;quot;. It&#039;s perfectly fine. No, really, I haven&#039;t noticed any problems with it.&lt;br /&gt;
&lt;br /&gt;
The BeagleBones with dead (worn out) eMMC need to boot from μSD card instead, or netboot if you&#039;re feeling adventurous.&lt;br /&gt;
&lt;br /&gt;
The &amp;quot;3.3V regulator patch&amp;quot; means the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; &amp;lt;strike&amp;gt;in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft&amp;lt;/strike&amp;gt; maybe still somewhere in the space.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed with a basic firmware image (debian stretch with customizations). You can reach it with &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777. There is a README file in the home directory, I might also put more details here if I get less lazy.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host port inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Supports Wayland but not X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=8556</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=8556"/>
		<updated>2018-05-06T10:40:25Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* TL;DR */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Bbb-zmattified.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated BeagleBones seek projects that can give their life meaning.&#039;&#039;&#039; ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do). Don&#039;t be afraid to play with it!&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Do you want a 14-channel 100 Msps logic analyzer? Just run [https://beaglelogic.readthedocs.io/en/latest/ BeagleLogic] on a BeagleBone!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
Also, check out my [https://github.com/mvduin/py-uio/#uio_pruss py-uio] project for directly working with the PRU subsystem (and various other peripherals) from python code. Poke me on IRC if you have questions.&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
There are currently several donated BeagleBone Black (rev C) boards with minor defects, donated by [[User:zmatt|my]] employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]:&lt;br /&gt;
* &amp;quot;boner&amp;quot;. Has 3.3V regulator patch, battery header soldered on, and shown running on battery at the top of the page. One I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
* &amp;quot;ham-015&amp;quot;. eMMC is dead.&lt;br /&gt;
* &amp;quot;ham-050&amp;quot;. eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;8m-094&amp;quot;. eMMC is dead. Has 3.3V regulator patch, battery header soldered on.&lt;br /&gt;
* &amp;quot;8c-085&amp;quot; aka &amp;quot;licht gebakken&amp;quot;. It&#039;s perfectly fine. No, really, I haven&#039;t noticed any problems with it.&lt;br /&gt;
&lt;br /&gt;
The BeagleBones with dead (worn out) eMMC need to boot from μSD card instead, or netboot if you&#039;re feeling adventurous.&lt;br /&gt;
&lt;br /&gt;
The &amp;quot;3.3V regulator patch&amp;quot; means the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; &amp;lt;strike&amp;gt;in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft&amp;lt;/strike&amp;gt; maybe still somewhere in the space.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed with a basic firmware image (debian stretch with customizations). You can reach it with &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777. There is a README file in the home directory, I might also put more details here if I get less lazy.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host port inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Supports Wayland but not X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=8555</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=8555"/>
		<updated>2018-05-06T10:26:12Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Description */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Bbb-zmattified.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated BeagleBones seek projects that can give their life meaning.&#039;&#039;&#039; ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do). Don&#039;t be afraid to play with it!&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Do you want a 14-channel 100 Msps logic analyzer? Just run [https://beaglelogic.readthedocs.io/en/latest/ BeagleLogic] on a BeagleBone!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
There are currently several donated BeagleBone Black (rev C) boards with minor defects, donated by [[User:zmatt|my]] employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]:&lt;br /&gt;
* &amp;quot;boner&amp;quot;. Has 3.3V regulator patch, battery header soldered on, and shown running on battery at the top of the page. One I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
* &amp;quot;ham-015&amp;quot;. eMMC is dead.&lt;br /&gt;
* &amp;quot;ham-050&amp;quot;. eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
* &amp;quot;8m-094&amp;quot;. eMMC is dead. Has 3.3V regulator patch, battery header soldered on.&lt;br /&gt;
* &amp;quot;8c-085&amp;quot; aka &amp;quot;licht gebakken&amp;quot;. It&#039;s perfectly fine. No, really, I haven&#039;t noticed any problems with it.&lt;br /&gt;
&lt;br /&gt;
The BeagleBones with dead (worn out) eMMC need to boot from μSD card instead, or netboot if you&#039;re feeling adventurous.&lt;br /&gt;
&lt;br /&gt;
The &amp;quot;3.3V regulator patch&amp;quot; means the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; &amp;lt;strike&amp;gt;in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft&amp;lt;/strike&amp;gt; maybe still somewhere in the space.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed with a basic firmware image (debian stretch with customizations). You can reach it with &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777. There is a README file in the home directory, I might also put more details here if I get less lazy.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host port inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Supports Wayland but not X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=8554</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=8554"/>
		<updated>2018-05-06T10:25:55Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Description */ Describe the new happy family&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Bbb-zmattified.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated BeagleBones seek projects that can give their life meaning.&#039;&#039;&#039; ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do). Don&#039;t be afraid to play with it!&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Do you want a 14-channel 100 Msps logic analyzer? Just run [https://beaglelogic.readthedocs.io/en/latest/ BeagleLogic] on a BeagleBone!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
There are currently several donated BeagleBone Black (rev C) boards with minor defects, donated by [[User:zmatt|my]] employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]:&lt;br /&gt;
 * &amp;quot;boner&amp;quot;. Has 3.3V regulator patch, battery header soldered on, and shown running on battery at the top of the page. One I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
 * &amp;quot;ham-015&amp;quot;. eMMC is dead.&lt;br /&gt;
 * &amp;quot;ham-050&amp;quot;. eMMC is dead. Has 3.3V regulator patch. USB mini-B and micro-HDMI ports have been desoldered.&lt;br /&gt;
 * &amp;quot;8m-094&amp;quot;. eMMC is dead. Has 3.3V regulator patch, battery header soldered on.&lt;br /&gt;
 * &amp;quot;8c-085&amp;quot; aka &amp;quot;licht gebakken&amp;quot;. It&#039;s perfectly fine. No, really, I haven&#039;t noticed any problems with it.&lt;br /&gt;
&lt;br /&gt;
The BeagleBones with dead (worn out) eMMC need to boot from μSD card instead, or netboot if you&#039;re feeling adventurous.&lt;br /&gt;
&lt;br /&gt;
The &amp;quot;3.3V regulator patch&amp;quot; means the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; &amp;lt;strike&amp;gt;in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft&amp;lt;/strike&amp;gt; maybe still somewhere in the space.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed with a basic firmware image (debian stretch with customizations). You can reach it with &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777. There is a README file in the home directory, I might also put more details here if I get less lazy.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host port inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Supports Wayland but not X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=8552</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=8552"/>
		<updated>2018-05-06T10:05:36Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* TL;DR */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Bbb-zmattified.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated BeagleBones seek projects that can give their life meaning.&#039;&#039;&#039; ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do). Don&#039;t be afraid to play with it!&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Do you want a 14-channel 100 Msps logic analyzer? Just run [https://beaglelogic.readthedocs.io/en/latest/ BeagleLogic] on a BeagleBone!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
&lt;br /&gt;
BeagleBone Black (rev C), donated by my employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]. It has one minor defect: one I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
&lt;br /&gt;
Like most of our BBBs it also has a small patch: the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft, along with some other documentation.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed with a basic firmware image (debian stretch with customizations). You can reach it with &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777. There is a README file in the home directory, I might also put more details here if I get less lazy.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host port inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Supports Wayland but not X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=8551</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=8551"/>
		<updated>2018-05-06T10:05:17Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* TL;DR */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Bbb-zmattified.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated BeagleBones seek projects that can give their life meaning. ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do). Don&#039;t be afraid to play with it!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Do you want a 14-channel 100 Msps logic analyzer? Just run [https://beaglelogic.readthedocs.io/en/latest/ BeagleLogic] on a BeagleBone!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
&lt;br /&gt;
BeagleBone Black (rev C), donated by my employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]. It has one minor defect: one I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
&lt;br /&gt;
Like most of our BBBs it also has a small patch: the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft, along with some other documentation.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed with a basic firmware image (debian stretch with customizations). You can reach it with &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777. There is a README file in the home directory, I might also put more details here if I get less lazy.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host port inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Supports Wayland but not X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=Nurdinn_Spring2018edition&amp;diff=8515</id>
		<title>Nurdinn Spring2018edition</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=Nurdinn_Spring2018edition&amp;diff=8515"/>
		<updated>2018-04-20T12:46:22Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Event&lt;br /&gt;
|Name=Nurdinn Spring2018edition&lt;br /&gt;
|Date=2018/05/03&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
&lt;br /&gt;
3..7 may 2018, save the date!&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
Add yourself to the attendee list below:&lt;br /&gt;
&lt;br /&gt;
* [[User:R3boot|r3boot]]&lt;br /&gt;
* [[User:buZz|buZz]]&lt;br /&gt;
* [[User:dreamer|dreamer]]&lt;br /&gt;
* [[User:zmatt|zmatt]]&lt;br /&gt;
* jinx?&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=VolksNurdInn_Bonanza&amp;diff=7845</id>
		<title>VolksNurdInn Bonanza</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=VolksNurdInn_Bonanza&amp;diff=7845"/>
		<updated>2017-04-30T23:48:59Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: add link to google maps&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Event&lt;br /&gt;
|Name=VolksNurdInn Bonanza&lt;br /&gt;
|Date=2017/05/05&lt;br /&gt;
|Location=Volkshuis&lt;br /&gt;
|Attendees=Dreamer, BuZz&lt;br /&gt;
}}&lt;br /&gt;
First nurd-inn in the [https://www.google.nl/maps/place/NURDspace new location]! Starting Thursday May 4th until Sunday May 7th.&lt;br /&gt;
&lt;br /&gt;
This might be the first time people spend the night in the volkshuis of the past 100 yrs.&lt;br /&gt;
&lt;br /&gt;
Coincides with 5th may celebrations in town, so unofficial pre-and-post-party for this :)&lt;br /&gt;
&lt;br /&gt;
== Attendees ==&lt;br /&gt;
&lt;br /&gt;
* [[User:dreamer|dreamer]]&lt;br /&gt;
* [[User:nooitaf|nooitaf]]&lt;br /&gt;
* [https://avatars1.githubusercontent.com/u/140660 madeddie]&lt;br /&gt;
* [[User:buZz|buZz]]&lt;br /&gt;
* [[User:zmatt|zmatt]]&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=Volkshuis&amp;diff=7844</id>
		<title>Volkshuis</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=Volkshuis&amp;diff=7844"/>
		<updated>2017-04-30T23:44:34Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;The Volkshuis &amp;lt;strike&amp;gt;will probably be&amp;lt;/strike&amp;gt; &#039;&#039;is&#039;&#039; the new location of our hackerspace. It&#039;s located at Vergersweg 22-24 in Wageningen.&lt;br /&gt;
&lt;br /&gt;
Below are some &#039;&#039;pre-invasion&#039;&#039; pictures and specs.&lt;br /&gt;
&lt;br /&gt;
&amp;lt;gallery&amp;gt;&lt;br /&gt;
&lt;br /&gt;
Image:lTlYt6z.jpg&lt;br /&gt;
Image:07 - 2RLBoin.jpg&lt;br /&gt;
Image:08 - fTseS2c.jpg&lt;br /&gt;
Image:09 - w7PbGzI.jpg&lt;br /&gt;
Image:10 - t4340eC.jpg&lt;br /&gt;
Image:11 - IYsrmwz.jpg&lt;br /&gt;
Image:12 - LCoTu0v.jpg&lt;br /&gt;
Image:13 - ICU8Thb.jpg&lt;br /&gt;
Image:14 - 5MaaMak.jpg&lt;br /&gt;
Image:15 - hnQVmHr.jpg&lt;br /&gt;
Image:16 - sOtGSFa.jpg&lt;br /&gt;
Image:17 - PsZaQF5.jpg&lt;br /&gt;
Image:18 - zNgYi9C.jpg&lt;br /&gt;
Image:19 - OcxKGL5.jpg&lt;br /&gt;
Image:20 - p9BsKAW.jpg&lt;br /&gt;
Image:21 - wdaWGQf.jpg&lt;br /&gt;
Image:01 - EbpncB3.jpg&lt;br /&gt;
Image:02 - 8iBHKc6.jpg&lt;br /&gt;
Image:03 - 8goTvSQ.jpg&lt;br /&gt;
Image:04 - iujNqMo.jpg&lt;br /&gt;
Image:05 - xPlh6Cy.jpg&lt;br /&gt;
Image:06 - ea8Blg3.jpg&lt;br /&gt;
&lt;br /&gt;
&amp;lt;/gallery&amp;gt;&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=VolksNurdInn_Bonanza&amp;diff=7843</id>
		<title>VolksNurdInn Bonanza</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=VolksNurdInn_Bonanza&amp;diff=7843"/>
		<updated>2017-04-30T23:27:18Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Attendees */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Event&lt;br /&gt;
|Name=VolksNurdInn Bonanza&lt;br /&gt;
|Date=2017/05/05&lt;br /&gt;
|Location=Volkshuis&lt;br /&gt;
|Attendees=Dreamer, BuZz&lt;br /&gt;
}}&lt;br /&gt;
First nurd-inn in the new location! Starting Thursday May 4th until Sunday May 7th.&lt;br /&gt;
&lt;br /&gt;
This might be the first time people spend the night in the volkshuis of the past 100 yrs.&lt;br /&gt;
&lt;br /&gt;
Coincides with 5th may celebrations in town, so unofficial pre-and-post-party for this :)&lt;br /&gt;
&lt;br /&gt;
== Attendees ==&lt;br /&gt;
&lt;br /&gt;
* [[User:dreamer|dreamer]]&lt;br /&gt;
* [[User:nooitaf|nooitaf]]&lt;br /&gt;
* [https://avatars1.githubusercontent.com/u/140660 madeddie]&lt;br /&gt;
* [[User:buZz|buZz]]&lt;br /&gt;
* [[User:zmatt|zmatt]]&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7558</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7558"/>
		<updated>2017-01-14T14:59:34Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Overview */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Bbb-zmattified.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated SBC seeks a project that can give its life meaning. ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do). Don&#039;t be afraid to play with it!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
&lt;br /&gt;
BeagleBone Black (rev C), donated by my employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]. It has one minor defect: one I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
&lt;br /&gt;
Like most of our BBBs it also has a small patch: the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft, along with some other documentation.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed with a basic firmware image (debian stretch with customizations). You can reach it with &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777. There is a README file in the home directory, I might also put more details here if I get less lazy.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host port inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Supports Wayland but not X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7557</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7557"/>
		<updated>2017-01-14T13:50:08Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Overview */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Bbb-zmattified.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated SBC seeks a project that can give its life meaning. ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do). Don&#039;t be afraid to play with it!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
&lt;br /&gt;
BeagleBone Black (rev C), donated by my employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]. It has one minor defect: one I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
&lt;br /&gt;
Like most of our BBBs it also has a small patch: the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft, along with some other documentation.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed with a basic firmware image (debian stretch with customizations). You can reach it with &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777. There is a README file in the home directory, I might also put more details here if I get less lazy.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host and device ports inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Supports Wayland but not X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7556</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7556"/>
		<updated>2017-01-14T13:41:44Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Processor subsystems */ mention wayland support for 3d&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Bbb-zmattified.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated SBC seeks a project that can give its life meaning. ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do). Don&#039;t be afraid to play with it!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
&lt;br /&gt;
BeagleBone Black (rev C), donated by my employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]. It has one minor defect: one I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
&lt;br /&gt;
Like most of our BBBs it also has a small patch: the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft, along with some other documentation.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed [http://pastebin.com/x5QzB18E via USB], I&#039;ll put more details here when I get less lazy. &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host and device ports inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Supports Wayland but not X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7555</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7555"/>
		<updated>2017-01-14T13:38:24Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* TL;DR */ mention a few interesting peripherals&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Bbb-zmattified.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated SBC seeks a project that can give its life meaning. ARM Cortex-A8, lots of I/O, rich set of peripherals (CAN, ADC, high-res PWM, etc), hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do). Don&#039;t be afraid to play with it!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
&lt;br /&gt;
BeagleBone Black (rev C), donated by my employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]. It has one minor defect: one I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
&lt;br /&gt;
Like most of our BBBs it also has a small patch: the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft, along with some other documentation.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed [http://pastebin.com/x5QzB18E via USB], I&#039;ll put more details here when I get less lazy. &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host and device ports inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Not supported by X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7554</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7554"/>
		<updated>2017-01-14T13:33:02Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Overview */ Arrange info based on importance&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Bbb-zmattified.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated SBC seeks a project that can give its life meaning. ARM Cortex-A8, lots of I/O, rich set of peripherals, hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do). Don&#039;t be afraid to play with it!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
&lt;br /&gt;
BeagleBone Black (rev C), donated by my employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]. It has one minor defect: one I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
&lt;br /&gt;
Like most of our BBBs it also has a small patch: the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft, along with some other documentation.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed [http://pastebin.com/x5QzB18E via USB], I&#039;ll put more details here when I get less lazy. &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777.&lt;br /&gt;
&lt;br /&gt;
The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; on the beaglebone for info on using it.&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host and device ports inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Not supported by X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7553</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7553"/>
		<updated>2017-01-14T13:28:54Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: Adds TL;DR section&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=boner&lt;br /&gt;
|Picture=Bbb-zmattified.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== TL;DR ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Donated SBC seeks a project that can give its life meaning. ARM Cortex-A8, lots of I/O, rich set of peripherals, hard real-time capability thanks to its pair of &amp;quot;PRU&amp;quot; cores (see [http://elinux.org/images/a/ac/What&#039;s_Old_Is_New-_A_6502-based_Remote_Processor.pdf these slides]] for an example of what they can do). Don&#039;t be afraid to play with it!&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
== Description ==&lt;br /&gt;
&lt;br /&gt;
BeagleBone Black (rev C), donated by my employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]. It has one minor defect: one I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
&lt;br /&gt;
Like most of our BBBs it also has a small patch: the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft, along with some other documentation.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host and device ports inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed [http://pastebin.com/x5QzB18E via USB], I&#039;ll put more details here when I get less lazy. &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777.  The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; for info on using it.&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Not supported by X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7552</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7552"/>
		<updated>2017-01-14T13:15:41Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Peripherals */ fix note on current i2c usage&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=bbb&lt;br /&gt;
|Picture=Bbb-zmattified.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== Description ==&lt;br /&gt;
&lt;br /&gt;
BeagleBone Black (rev C), donated by my employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]. It has one minor defect: one I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
&lt;br /&gt;
Like most of our BBBs it also has a small patch: the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft, along with some other documentation.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host and device ports inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed [http://pastebin.com/x5QzB18E via USB], I&#039;ll put more details here when I get less lazy. &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777.  The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; for info on using it.&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Not supported by X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C2&#039;&#039; is enabled by default &amp;lt;strike&amp;gt;and used for automatic [http://beagleboard.org/cape CAPE] detection&amp;lt;/strike&amp;gt; but it can also be used for other purposes or disabled entirely. (It&#039;s currently not configured to support CAPE autodetection; it still enables &#039;&#039;I2C2&#039;&#039; however to support the OLED display.)&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7551</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7551"/>
		<updated>2017-01-14T13:00:34Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Overview */ add short note on OLED display&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=bbb&lt;br /&gt;
|Picture=Bbb-zmattified.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== Description ==&lt;br /&gt;
&lt;br /&gt;
BeagleBone Black (rev C), donated by my employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]. It has one minor defect: one I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
&lt;br /&gt;
Like most of our BBBs it also has a small patch: the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft, along with some other documentation.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host and device ports inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed [http://pastebin.com/x5QzB18E via USB], I&#039;ll put more details here when I get less lazy. &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777.  The OLED screen attached to it belongs to [[User:buZz|buZz]], see &amp;lt;code&amp;gt;~dev/oled/README&amp;lt;/code&amp;gt; for info on using it.&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Not supported by X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C1&#039;&#039; is enabled by default and used for automatic [http://beagleboard.org/cape CAPE] detection but it can also be used for other purposes or disabled entirely.&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7512</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7512"/>
		<updated>2016-12-04T13:52:27Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: /* Overview */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=bbb&lt;br /&gt;
|Picture=Bbb-zmattified.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== Description ==&lt;br /&gt;
&lt;br /&gt;
BeagleBone Black (rev C), donated by my employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]. It has one minor defect: one I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
&lt;br /&gt;
Like most of our BBBs it also has a small patch: the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; in [[User:Cha0z97|cha0z97]]&#039;s top-left drawer, buried under some cruft, along with some other documentation.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host and device ports inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
The bbb has been recently (4-12-2016) been reflashed [http://pastebin.com/x5QzB18E via USB], I&#039;ll put more details here when I get less lazy. &amp;lt;code&amp;gt;ssh dev@boner&amp;lt;/code&amp;gt;, password 777.&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Not supported by X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C1&#039;&#039; is enabled by default and used for automatic [http://beagleboard.org/cape CAPE] detection but it can also be used for other purposes or disabled entirely.&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7371</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7371"/>
		<updated>2016-08-17T16:22:25Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: Now then&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Project&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=bbb&lt;br /&gt;
|Picture=Bbb-zmattified.jpg&lt;br /&gt;
|Location=Space&lt;br /&gt;
}}&lt;br /&gt;
== Description ==&lt;br /&gt;
&lt;br /&gt;
BeagleBone Black (rev C), donated by my employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]. It has one minor defect: one I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
&lt;br /&gt;
Like most of our BBBs it also has a small patch: the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; in [[User:Cha0z97|cha0z97]]&#039;s drawer, along with some other documentation.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host and device ports inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
The bbb has been flashed [http://pastebin.com/x5QzB18E via USB] with [https://rcn-ee.com/rootfs/bb.org/testing/2016-03-27/iot/ jessie-8.3-iot-2016-03-27]. Latest images can be found [http://elinux.org/Beagleboard:BeagleBoneBlack_Debian#Jessie_Snapshot_iot here]. I personally normally start with a &amp;quot;console&amp;quot; image, which is extremely minimalistic and intended for those who prefer to start with a blank slate and install the stuff they need themselves. For convenience however I&#039;ve flashed the &amp;quot;iot&amp;quot; image which has no GUI but does include the webserver and cloud9 IDE. Changes I&#039;ve made:&lt;br /&gt;
* rootfs partition starts at offset 4 MB instead of 1 MB to align it with eMMC allocation group boundary.&lt;br /&gt;
* debian stretch has been added as low-priority APT repository and systemd has been upgraded. jessie&#039;s systemd is too ancient to e.g. make systemd-networkd usable, but upgrading the whole system seemed too risky.&lt;br /&gt;
* switched from connman to systemd-networkd since I had some networking issues but know absolutely nothing about connman. I haven&#039;t reenabled USB networking since it seemed pointless, but it would be easy to do so if desired.&lt;br /&gt;
* set APT setting to disable automatically installing packages &amp;quot;recommended&amp;quot; by installed packages since this tends to pull in a lot of crap.&lt;br /&gt;
* removed a lot of crap that got automatically installed (including parts of X11).&lt;br /&gt;
&lt;br /&gt;
I&#039;ve made some attempts at getting the web interface functional. It assumed you use it via USB networking rather than Ethernet, and used its hardcoded IP (192.168.7.1) in many places. I&#039;ve replaced those with the hostname, which at least made the link to the cloud9 IDE work. Bonescript briefly worked but then broke again, dunno why.&lt;br /&gt;
&lt;br /&gt;
URL of web interface is just [http://bbb/ http://bbb/], or if the local DNS has stale records again use [http://bbb.local/ http://bbb.local/] (avahi to the rescue!). Cloud9 IDE is on port 9000. SSH login/password is debian/777.&lt;br /&gt;
&lt;br /&gt;
I&#039;ve also written a bunch of utility scripts:&lt;br /&gt;
* &amp;lt;code&amp;gt;gpio-parse&amp;lt;/code&amp;gt; can convert between various ways of identifying GPIOs&lt;br /&gt;
* &amp;lt;code&amp;gt;sudo gpio-export&amp;lt;/code&amp;gt; exports a GPIO via sysfs (accepts any format that &amp;lt;code&amp;gt;gpio-parse&amp;lt;/code&amp;gt;, prints the sysfs paths)&lt;br /&gt;
* &amp;lt;code&amp;gt;sudo gpio-unexport&amp;lt;/code&amp;gt; removes such exports&lt;br /&gt;
* &amp;lt;code&amp;gt;sudo show-pins&amp;lt;/code&amp;gt; detailed overview of pin config and usage&lt;br /&gt;
* &amp;lt;code&amp;gt;~/charger-info.pl&amp;lt;/code&amp;gt; shows (some) status info of the battery charger state&lt;br /&gt;
* &amp;lt;code&amp;gt;/etc/pmic-config.sh&amp;lt;/code&amp;gt; configures the PMIC with more liberal charger settings. Invoked at startup by &amp;lt;code&amp;gt;/etc/systemd/system/pmic-config.service&amp;lt;/code&amp;gt;.&lt;br /&gt;
&lt;br /&gt;
Except for &amp;quot;show-pins&amp;quot;, all of these were written from scratch on this BBB so you may want to make a backup if you intend to reflash the BBB.&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Not supported by X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C1&#039;&#039; is enabled by default and used for automatic [http://beagleboard.org/cape CAPE] detection but it can also be used for other purposes or disabled entirely.&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7370</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7370"/>
		<updated>2016-08-17T16:21:02Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: Undo revision 7369, doesn&amp;#039;t help&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Inventory&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Seeking purpose&lt;br /&gt;
|Hostname=bbb&lt;br /&gt;
|Picture=Bbb-zmattified.jpg&lt;br /&gt;
}}&lt;br /&gt;
== Description ==&lt;br /&gt;
&lt;br /&gt;
BeagleBone Black (rev C), donated by my employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]. It has one minor defect: one I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
&lt;br /&gt;
Like most of our BBBs it also has a small patch: the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; in [[User:Cha0z97|cha0z97]]&#039;s drawer, along with some other documentation.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host and device ports inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
The bbb has been flashed [http://pastebin.com/x5QzB18E via USB] with [https://rcn-ee.com/rootfs/bb.org/testing/2016-03-27/iot/ jessie-8.3-iot-2016-03-27]. Latest images can be found [http://elinux.org/Beagleboard:BeagleBoneBlack_Debian#Jessie_Snapshot_iot here]. I personally normally start with a &amp;quot;console&amp;quot; image, which is extremely minimalistic and intended for those who prefer to start with a blank slate and install the stuff they need themselves. For convenience however I&#039;ve flashed the &amp;quot;iot&amp;quot; image which has no GUI but does include the webserver and cloud9 IDE. Changes I&#039;ve made:&lt;br /&gt;
* rootfs partition starts at offset 4 MB instead of 1 MB to align it with eMMC allocation group boundary.&lt;br /&gt;
* debian stretch has been added as low-priority APT repository and systemd has been upgraded. jessie&#039;s systemd is too ancient to e.g. make systemd-networkd usable, but upgrading the whole system seemed too risky.&lt;br /&gt;
* switched from connman to systemd-networkd since I had some networking issues but know absolutely nothing about connman. I haven&#039;t reenabled USB networking since it seemed pointless, but it would be easy to do so if desired.&lt;br /&gt;
* set APT setting to disable automatically installing packages &amp;quot;recommended&amp;quot; by installed packages since this tends to pull in a lot of crap.&lt;br /&gt;
* removed a lot of crap that got automatically installed (including parts of X11).&lt;br /&gt;
&lt;br /&gt;
I&#039;ve made some attempts at getting the web interface functional. It assumed you use it via USB networking rather than Ethernet, and used its hardcoded IP (192.168.7.1) in many places. I&#039;ve replaced those with the hostname, which at least made the link to the cloud9 IDE work. Bonescript briefly worked but then broke again, dunno why.&lt;br /&gt;
&lt;br /&gt;
URL of web interface is just [http://bbb/ http://bbb/], or if the local DNS has stale records again use [http://bbb.local/ http://bbb.local/] (avahi to the rescue!). Cloud9 IDE is on port 9000. SSH login/password is debian/777.&lt;br /&gt;
&lt;br /&gt;
I&#039;ve also written a bunch of utility scripts:&lt;br /&gt;
* &amp;lt;code&amp;gt;gpio-parse&amp;lt;/code&amp;gt; can convert between various ways of identifying GPIOs&lt;br /&gt;
* &amp;lt;code&amp;gt;sudo gpio-export&amp;lt;/code&amp;gt; exports a GPIO via sysfs (accepts any format that &amp;lt;code&amp;gt;gpio-parse&amp;lt;/code&amp;gt;, prints the sysfs paths)&lt;br /&gt;
* &amp;lt;code&amp;gt;sudo gpio-unexport&amp;lt;/code&amp;gt; removes such exports&lt;br /&gt;
* &amp;lt;code&amp;gt;sudo show-pins&amp;lt;/code&amp;gt; detailed overview of pin config and usage&lt;br /&gt;
* &amp;lt;code&amp;gt;~/charger-info.pl&amp;lt;/code&amp;gt; shows (some) status info of the battery charger state&lt;br /&gt;
* &amp;lt;code&amp;gt;/etc/pmic-config.sh&amp;lt;/code&amp;gt; configures the PMIC with more liberal charger settings. Invoked at startup by &amp;lt;code&amp;gt;/etc/systemd/system/pmic-config.service&amp;lt;/code&amp;gt;.&lt;br /&gt;
&lt;br /&gt;
Except for &amp;quot;show-pins&amp;quot;, all of these were written from scratch on this BBB so you may want to make a backup if you intend to reflash the BBB.&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Not supported by X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C1&#039;&#039; is enabled by default and used for automatic [http://beagleboard.org/cape CAPE] detection but it can also be used for other purposes or disabled entirely.&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
	<entry>
		<id>https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7369</id>
		<title>BeagleBone</title>
		<link rel="alternate" type="text/html" href="https://nurdspace.nl/index.php?title=BeagleBone&amp;diff=7369"/>
		<updated>2016-08-17T16:19:34Z</updated>

		<summary type="html">&lt;p&gt;Zmatt: Make it show up in projects list&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;{{Inventory&lt;br /&gt;
|Name=BeagleBone Black&lt;br /&gt;
|Owner=User:zmatt&lt;br /&gt;
|Status=Active&lt;br /&gt;
|Hostname=bbb&lt;br /&gt;
|Picture=Bbb-zmattified.jpg&lt;br /&gt;
}}&lt;br /&gt;
== Description ==&lt;br /&gt;
&lt;br /&gt;
BeagleBone Black (rev C), donated by my employer [http://dutchdutch.com/ Dutch &amp;amp; Dutch]. It has one minor defect: one I/O pin (P9.26 / GPIO 0.14) has been damaged, probably by overvoltage, and has become unusable. I&#039;ve stuffed it with polycaprolactone to clearly mark it and avoid accidental use.&lt;br /&gt;
&lt;br /&gt;
Like most of our BBBs it also has a small patch: the separate regulator for &amp;quot;VDD_3V3B&amp;quot; has been removed and the voltage rail has been tied to the &amp;quot;VDD_3V3A&amp;quot; instead, which means it has a single unified 3.3V rail. This patch was done to avoid the problem where the 3V3B remains enabled too long during poweroff and indefinitely if the BBB is supplied via battery power. With this patch the BBB can be safely powered via its battery terminals (Li-ion/LiPo, BBB has integrated charger). An obvious side-effect is that less power can be drawn from the BBB&#039;s 3.3V supply by external hardware.  See [http://elinux.org/BeagleBone_Power_Management here] for more info on BBB power supply infrastructure.&lt;br /&gt;
&lt;br /&gt;
Information on pin functions can be found in [https://goo.gl/Jkcg0w this spreadsheet].  Laminated printouts of the P9 and P8 tabs are &amp;lt;strike&amp;gt;somewhere in the space&amp;lt;/strike&amp;gt; in [[User:Cha0z97|cha0z97]]&#039;s drawer, along with some other documentation.  If you intend to connect anything to the BBB keep these nearby for reference, and read the hardware safety notes below!  For proper orientation, have the Ethernet connector facing up. P9 is then the connector on the left and P8 is on the right.&lt;br /&gt;
&lt;br /&gt;
== Playing with it ==&lt;br /&gt;
&lt;br /&gt;
=== Overview ===&lt;br /&gt;
&lt;br /&gt;
Battery pack has been attached, can be charged via USB or the 5V DC barrel jack (1A or more recommended, but less should work too). Use script mentioned below to check its status. The battery will not last as long as you&#039;d expect it to since there is no boost conversion and the system will shut off when the 3.3V supplies lose regulation. Since the pack is quite big it can still run for many hours though. Running on battery power will render the USB host and device ports inoperable due to invalid V&amp;lt;sub&amp;gt;BUS&amp;lt;/sub&amp;gt; level. Instead of an actual temperature sensor there&#039;s a resistor on the battery header telling the charger the temperature is okay for charging. Be careful not to use this setup outside the safe temperature range for charging the battery pack (0 - 45 ͏°C).&lt;br /&gt;
&lt;br /&gt;
The bbb has been flashed [http://pastebin.com/x5QzB18E via USB] with [https://rcn-ee.com/rootfs/bb.org/testing/2016-03-27/iot/ jessie-8.3-iot-2016-03-27]. Latest images can be found [http://elinux.org/Beagleboard:BeagleBoneBlack_Debian#Jessie_Snapshot_iot here]. I personally normally start with a &amp;quot;console&amp;quot; image, which is extremely minimalistic and intended for those who prefer to start with a blank slate and install the stuff they need themselves. For convenience however I&#039;ve flashed the &amp;quot;iot&amp;quot; image which has no GUI but does include the webserver and cloud9 IDE. Changes I&#039;ve made:&lt;br /&gt;
* rootfs partition starts at offset 4 MB instead of 1 MB to align it with eMMC allocation group boundary.&lt;br /&gt;
* debian stretch has been added as low-priority APT repository and systemd has been upgraded. jessie&#039;s systemd is too ancient to e.g. make systemd-networkd usable, but upgrading the whole system seemed too risky.&lt;br /&gt;
* switched from connman to systemd-networkd since I had some networking issues but know absolutely nothing about connman. I haven&#039;t reenabled USB networking since it seemed pointless, but it would be easy to do so if desired.&lt;br /&gt;
* set APT setting to disable automatically installing packages &amp;quot;recommended&amp;quot; by installed packages since this tends to pull in a lot of crap.&lt;br /&gt;
* removed a lot of crap that got automatically installed (including parts of X11).&lt;br /&gt;
&lt;br /&gt;
I&#039;ve made some attempts at getting the web interface functional. It assumed you use it via USB networking rather than Ethernet, and used its hardcoded IP (192.168.7.1) in many places. I&#039;ve replaced those with the hostname, which at least made the link to the cloud9 IDE work. Bonescript briefly worked but then broke again, dunno why.&lt;br /&gt;
&lt;br /&gt;
URL of web interface is just [http://bbb/ http://bbb/], or if the local DNS has stale records again use [http://bbb.local/ http://bbb.local/] (avahi to the rescue!). Cloud9 IDE is on port 9000. SSH login/password is debian/777.&lt;br /&gt;
&lt;br /&gt;
I&#039;ve also written a bunch of utility scripts:&lt;br /&gt;
* &amp;lt;code&amp;gt;gpio-parse&amp;lt;/code&amp;gt; can convert between various ways of identifying GPIOs&lt;br /&gt;
* &amp;lt;code&amp;gt;sudo gpio-export&amp;lt;/code&amp;gt; exports a GPIO via sysfs (accepts any format that &amp;lt;code&amp;gt;gpio-parse&amp;lt;/code&amp;gt;, prints the sysfs paths)&lt;br /&gt;
* &amp;lt;code&amp;gt;sudo gpio-unexport&amp;lt;/code&amp;gt; removes such exports&lt;br /&gt;
* &amp;lt;code&amp;gt;sudo show-pins&amp;lt;/code&amp;gt; detailed overview of pin config and usage&lt;br /&gt;
* &amp;lt;code&amp;gt;~/charger-info.pl&amp;lt;/code&amp;gt; shows (some) status info of the battery charger state&lt;br /&gt;
* &amp;lt;code&amp;gt;/etc/pmic-config.sh&amp;lt;/code&amp;gt; configures the PMIC with more liberal charger settings. Invoked at startup by &amp;lt;code&amp;gt;/etc/systemd/system/pmic-config.service&amp;lt;/code&amp;gt;.&lt;br /&gt;
&lt;br /&gt;
Except for &amp;quot;show-pins&amp;quot;, all of these were written from scratch on this BBB so you may want to make a backup if you intend to reflash the BBB.&lt;br /&gt;
&lt;br /&gt;
=== Hardware safety notes ===&lt;br /&gt;
&lt;br /&gt;
The expansion header pins connect to the processor without any real protection, and being careless can destroy an IO or the entire processor.&lt;br /&gt;
&lt;br /&gt;
The digital I/Os are 3.3V and are &#039;&#039;&#039;NOT&#039;&#039;&#039; 5V-tolerant.&lt;br /&gt;
&lt;br /&gt;
The analog inputs are &#039;&#039;&#039;max 1.8V&#039;&#039;&#039;.  Due to a hardware erratum they may be briefly shorted together and/or to vdd or ground during power-up, hence it is recommended to avoid connecting them to low-impedance outputs (e.g. opamps) without a series resistor.&lt;br /&gt;
&lt;br /&gt;
Avoid injecting current into IOs when the beaglebone is powered off.  In particular, the digital I/Os are &#039;&#039;&#039;NOT&#039;&#039;&#039; 3.3V-tolerant when the 3.3V supply is off.&lt;br /&gt;
&lt;br /&gt;
Some pins on the expansion header are used by the on-board eMMC, and must not be touched. On the expansion header overview printouts they are clearly marked &amp;quot;eMMC&amp;quot;. If you really need them for other purposes this is still possible, but it requires booting via other means (e.g. μSD or netboot) and disabling the eMMC. Ask me (zmatt) for details if you ever need them.&lt;br /&gt;
&lt;br /&gt;
The last 16 pins of header P8 are sampled at power-on to determine boot configuration. They have weak (100KΩ) on-board pull up/down resistors. They can be freely used afterwards, but be careful not to meddle with them during power-on unless altering the boot config is intended. They are not resampled at reset, only at power-on.&lt;br /&gt;
&lt;br /&gt;
=== Big buttons ===&lt;br /&gt;
&lt;br /&gt;
The BBB has three pushbuttons:&lt;br /&gt;
* (S3) power button, next to the ethernet connector. Powers the system on when off. Shuts down the system when on (assuming proper OS config, since the PMIC obviously just sends an event). Hold for ~8 seconds to forcibly power cycle the system.&lt;br /&gt;
* (S1) reset button, next to the power button.&lt;br /&gt;
* (S2) boot button, somewhat nearby the μSD card slot. Pulls down pin 42 (&amp;quot;lcd_data2&amp;quot; / gpio 2.08) with 100Ω. If held during power-on this changes the boot device order from { eMMC, μSD, UART, USB } to { SPI, μSD, USB, UART }. This allows you to reflash the BBB via μSD or USB if the eMMC is hosed.&lt;br /&gt;
&lt;br /&gt;
All three are [http://www.digikey.com/product-detail/en/c-k-components/KMR231GLFS/401-1429-1-ND/550464 annoying tiny buttons], but you can instead connect a more comfortable button between ground and the appropriate expansion header pin:&lt;br /&gt;
* (S3) power button: P9.09&lt;br /&gt;
* (S1) reset button: P9.10&lt;br /&gt;
* (S2) boot button: P8.43 (use 100Ω - 10KΩ series resistor for safety since pin may be configured as output)&lt;br /&gt;
&lt;br /&gt;
== Hardware capabilities ==&lt;br /&gt;
&lt;br /&gt;
=== BeagleBone Black components ===&lt;br /&gt;
&lt;br /&gt;
* TI [http://www.ti.com/product/AM3358 AM3358] ARM-based SoC&lt;br /&gt;
* 512 MB DDR3L-800 memory&lt;br /&gt;
* 4 GB eMMC flash (either Micron [http://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/EMMC_Series.pdf MTFC4GLDEA-0M WT] or Kingston [http://docs-europe.electrocomponents.com/webdocs/12b9/0900766b812b9eb5.pdf KE4CN2H5A-A58])&lt;br /&gt;
* SMSC/Microchip [http://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf LAN8710A] 100BASE-TX Ethernet PHY&lt;br /&gt;
* NXP [http://www.mouser.com/catalog/specsheets/NXP_TDA19988.pdf TDA19988] HDMI framer&lt;br /&gt;
* TI [http://www.ti.com/product/TPS65217 TPS65217] power-management IC with Li-ion charger&lt;br /&gt;
* small I²C EEPROM for board identification&lt;br /&gt;
&lt;br /&gt;
Unless mentioned otherwise, all the stuff below are features of the AM3358.&lt;br /&gt;
&lt;br /&gt;
=== Processor subsystems ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Main CPU:&#039;&#039;&#039; 1 GHz Cortex-A8 with NEON, 32KB L1 icache, 32 KB L1 dcache, 256 KB L2 cache. Subsystem includes a small local interconnect, 64 KB of private SRAM, interrupt controller, and debug infrastructure. In its memory map, the private SRAM is directly adjacent to the shared 64 KB on-chip SRAM, allowing boot code to treat it as a single contiguous 128 KB SRAM for most purposes.&lt;br /&gt;
* &#039;&#039;&#039;3D GPU:&#039;&#039;&#039; PowerVR SGX-530. Requires non-mainlined open source kernel drivers and proprietary userspace libraries (no usage/redistribution restrictions). Supports OpenGL ES 1 and 2. Plenty of [http://powervr-graphics.github.io/Native_SDK/ examples]. Not supported by X11.&amp;lt;br&amp;gt;&lt;br /&gt;
* &#039;&#039;&#039;Wakeup controller:&#039;&#039;&#039; Cortex-M3 inside the always-on &amp;quot;wakeup domain&amp;quot;. It has no ROM code hence needs to be initialized by the cortex-A8, after which it is available to assist in transitioning to/from suspend and other low power states, especially those where the cortex-A8 is powered off. It can also be programmed freely, but it has limited RAM and only has access to peripherals in the wakeup domain.&lt;br /&gt;
* &#039;&#039;&#039;Programmable Real-time Unit&#039;&#039;&#039;: Two 200 MHz &#039;&#039;PRU&#039;&#039; cores, ideal for code with strict timing or ultra low-latency requirements, contained in a subsystem together with local SRAM, an interrupt controller, and some peripherals.&lt;br /&gt;
&lt;br /&gt;
=== Memory / storage ===&lt;br /&gt;
&lt;br /&gt;
Peripheral names shown in italic.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;EMIF&#039;&#039;: 512 MB DDR3L-800.&lt;br /&gt;
* &#039;&#039;MMC0&#039;&#039;: μSD card slot (4-bit, max 48 MHz).&lt;br /&gt;
* &#039;&#039;MMC1&#039;&#039;: 4 GB on-board eMMC (8-bit, 48 MHz). Also connects to P8, see hardware safety notes.&lt;br /&gt;
* &#039;&#039;MMC2&#039;&#039;: unused MMC/SD/SDIO controller (max 8-bit, max 48 MHz) accessible via expansion headers.&lt;br /&gt;
* &#039;&#039;GPMC&#039;&#039;: 8/16-bit bus controller (SRAM, NOR/NAND flash), pin-conflicts with eMMC, supports BCH-4/8/16 error correction codes for raw NAND flash including error location (&#039;&#039;ELM&#039;&#039;).&lt;br /&gt;
&lt;br /&gt;
There are also SRAMs embedded in various subsystems and 64 KB of shared SRAM (&#039;&#039;OCMC&#039;&#039;) for general use.&lt;br /&gt;
&lt;br /&gt;
A very flexible high-bandwidth DMA controller (&#039;&#039;EDMA&#039;&#039;) is available to transfer data between memories or to/from peripherals on software request or in response to hardware events. Some peripherals (e.g. Ethernet, &#039;&#039;LCDC&#039;&#039;) use integrated DMA instead.&lt;br /&gt;
&lt;br /&gt;
=== Peripherals ===&lt;br /&gt;
&lt;br /&gt;
Note: this lists the functionality available on the BBB regardless of whether any software example exists. Not all peripherals have kernel drivers, and the drivers that do exist may support only a subset of the peripheral&#039;s functionality. In most cases however you can just mmap the peripheral registers (using /dev/mem or [http://pastebin.com/GrHwgYiR UIO]) and use them directly like you would on a microcontroller. This is usually also a lot more efficient than having to go through the kernel. You can also receive IRQs in linux userspace using UIO, and if you&#039;re sufficiently nuts (like me) even set up DMA from userspace. For real-time needs you can run code on the two &amp;quot;PRU&amp;quot; cores, which can also access all peripherals and receive IRQs from many of them. Not all I/O listed can be used at the same time due to pinmux restrictions.&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;USB&#039;&#039;&#039;: USB subsystem with two Mentor &amp;quot;musbhdrc&amp;quot; USB 2.0 high-speed dual-role/OTG controller cores glued to TI custom PHYs and a complicated DMA controller. Known to be fickle at times. Officially used to provide one mini-B device port (&#039;&#039;USB0&#039;&#039;) and one host port (&#039;&#039;USB1&#039;&#039;), but this could be hacked into two host or two device ports with some creativity. A slightly odd feature is that &#039;&#039;UART2&#039;&#039; and &#039;&#039;UART3&#039;&#039; can also be routed to the data pins of &#039;&#039;USB0&#039;&#039; and &#039;&#039;USB1&#039;&#039; respectively, which then use standard 3.3V CMOS drivers instead of USB signalling.&lt;br /&gt;
* &#039;&#039;&#039;Ethernet&#039;&#039;&#039;: The AM335x has an Ethernet switch subsystem with two gigabit ports, but only one port is usable on the BeagleBone and it connects to a 100Mbit PHY. Some guy managed to patch a gigabit phy onto it but I would not recommend attempting to recreate that epic hack. (Get a [http://beagleboard.org/enhanced BBE] for that)&lt;br /&gt;
* &#039;&#039;&#039;Video out:&#039;&#039;&#039; &#039;&#039;LCDC&#039;&#039; display controller, max resolution 2048×2048 pixels, up to 24-bit color, max 126 MHz pixel clock. Connects to TDA19988 HDMI framer (max 16-bit color) and to expansion header P8. Can also directly drive passive-matrix screens, and various bus protocols typically used to interface with character displays (e.g. HD44780).&lt;br /&gt;
* &#039;&#039;&#039;Audio&#039;&#039;&#039;: Two audio serial ports (&#039;&#039;ASP0&#039;&#039;, &#039;&#039;ASP1&#039;&#039;) supporting I²S or up to 16 channels/pin TDM in master or slave mode. Highly configurable formatting. Can also be configured in &amp;quot;burst mode&amp;quot; for non-audio data (SPI-ish). Can use the 24 MHz main oscillator as master clock or use one supplied externally. The BBB has a 24.576 MHz oscillator which drives it signal onto pin 107 (P9.25) for use by &#039;&#039;ASP0&#039;&#039; on the BBB and/or external hardware as master clock for standard 48 kHz sample rate. Its output-enable is under software control and disabled by default to avoid conflicting with alternate uses of P9.25. &#039;&#039;ASP0&#039;&#039; also connects to the HDMI framer to provide audio output over HDMI.&lt;br /&gt;
* &#039;&#039;&#039;UART&#039;&#039;&#039;: 6 fancy UARTs which also support various IR protocols, and another simple but high-speed UART (max 12 Mbaud) located in the PRU subsystem. &#039;&#039;UART0&#039;&#039; is used as console port, has a 6-pin header compatible with FTDI cables (only GND, RxD, TxD connected) and on-board 5V-tolerant isolation buffer to avoid damaging the cpu if a cable is connected while the BBB is powered off. The remaining ports are accessible via P9 and P8, including hw flow control. &#039;&#039;UART1&#039;&#039; RxD is however lost due to damaged pin (but TxD can still be used).&lt;br /&gt;
* &#039;&#039;&#039;SPI&#039;&#039;&#039;: Two SPI ports on P9: &#039;&#039;SPI0&#039;&#039; with one hw chip select and &#039;&#039;SPI1&#039;&#039; with two (although gpio chip selects are a fine alternative in master mode for most purposes). Supports 48 MHz clock or integer divisions thereof. &#039;&#039;SPI0&#039;&#039; can be used as boot device if a compatible flash is connected.&lt;br /&gt;
* &#039;&#039;&#039;I²C&#039;&#039;&#039;: Three standard (100 kHz) / fast (400 kHz) I²C ports: two (&#039;&#039;I2C1&#039;&#039; and &#039;&#039;I2C2&#039;&#039;) accessible on P9, while &#039;&#039;I2C0&#039;&#039; connects to local devices (PMIC, identification EEPROM, HDMI framer) and is not accessible via headers. &#039;&#039;I2C1&#039;&#039; is enabled by default and used for automatic [http://beagleboard.org/cape CAPE] detection but it can also be used for other purposes or disabled entirely.&lt;br /&gt;
* &#039;&#039;&#039;CAN&#039;&#039;&#039;: Two CAN controllers (Bosch DCAN) on P9, but &#039;&#039;CAN1&#039;&#039; transmit is lost due to damaged pin hence it is limited to passive bus sniffing. Max 1 Mbps. External transceiver required.&lt;br /&gt;
* &#039;&#039;&#039;GPIO&#039;&#039;&#039;: Lots. Pretty much any pin can be used as GPIO, with support for debouncing and edge- or level-triggered interrupts. Any subset of the 32 pins of a GPIO bank can be set or cleared atomically with a single write. Inputs on &#039;&#039;GPIO0&#039;&#039; can wake the system from suspend.&lt;br /&gt;
* &#039;&#039;&#039;ADC&#039;&#039;&#039;: 8-channel 12-bit ADC, 7 of which available on P9. Programmable sequencer, including differential measurements. Can inject a measurement sequence on various triggers. Some pins can be driven high or low during sequencer steps to allow direct connection of 4- or 5-wire resistive touchscreens (with support for waking system from suspend on pen touch). See hardware safety notes on this page.&lt;br /&gt;
* &#039;&#039;&#039;PWM&#039;&#039;&#039;: There are three dedicated PWM peripherals, each with two outputs, 16-bit counter with programmable limit running at max 100 MHz, two match registers with programmable actions, &amp;quot;dead time&amp;quot; generation for complementary outputs, and optional output chopper said to be &amp;quot;useful for pulse transformer gate drives&amp;quot;. The modules can synchronize with each other with programmable phase difference. &#039;&#039;PWM0&#039;&#039; also has external sync in and out. Output &amp;quot;A&amp;quot; of each PWM module also has a programmable delay line for ultrafine duty cycle or phase adjustment (fraction of a nanosecond). In addition, the four capture modules and timers 4-7 can be configured as PWM outputs, for a total of 14 hardware PWM outputs. One (&#039;&#039;CAP1&#039;&#039;) is not accessible on the expansion headers (though you can route it to the console tx pin or one of the JTAG pads), while the remaining 13 are (and usable simultaneously).&lt;br /&gt;
&lt;br /&gt;
... work in progress ...&lt;/div&gt;</summary>
		<author><name>Zmatt</name></author>
	</entry>
</feed>