FPGA workshop: Difference between revisions

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{{Event
{{Event
|Name=hands-on FPGA
|Name=hands-on FPGA
|Date=2015/02/14
|Date=somewhere in 2015
|Location=@space
|Location=@space
|Contact=theo
|Contact=theo

Revision as of 03:51, 8 February 2015

FPGA workshop
Name hands-on FPGA
Date somewhere in 2015
DateEnd
Location @space
Contact theo
Attendees User:buzz, Dennis

A two-day hands-on workshop FPGA programming.

Hardware: an Altera cyclone FPGA development kit such as Terasic de0 nano (http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593) or (preferably) Bemicro CV ( http://parts.arrow.com/item/detail/arrow-development-tools/bemicrocv#ypJJ).

  • note* I've tried to order Bemicro CV's as that would be better value (cyclone V instead of cyclone IV and 128MB instead of 32MB RAM), but the order got bounced. They go in and out of stock constantly, so i'll try again later

Topics include

  • Recap of basic logic design principles
  • FPGA hardware architecture, logic blocks, look-up tables, memory and multipliers
  • FPGA resource constraints: routing, logic blocks, IO limitations
  • Hard & Soft IP and licensing
  • Installing Quartus on a linux machine
  • Design project workflow
  • Basic (V)HDL
  • Nios IIe system builder.
  • Altera vs Xilinx vs Lattice vs .....

Requirements

Some understanding of logic circuitry design principles, a supported (Altera) FPGA development kit and access to a (linux) computer for running the Quartus software

Costs

Free as in free beer and free speech, but limited to the consumables that you bring yourself ;-)

Venue

  • Diedenoort, Wageningen

Extra

Date and supported development kits are tentative, and will be fixed at least 8 weeks before workshop. If necessary we can organize a group-buy.

If you're interested in joining please PM me at the0 @ #nurds (irc.oftc.net) OR reply to my mail to the mailing list. It would be useful to know how much you know about digital circuit design as well

Want to attend

Some other date, not feb 14 Anus probably +1 (or 2) with some fpga bits and bobs